A transistor structure includes a substrate, a gate conductive region, a gate dielectric layer and a first conductive region. At least a portion of the gate conductive region is disposed below a surface of the substrate. The gate dielectric layer surrounds a bottom wall and sidewalls of the gate conductive region. A bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.

A transistor includes a first well region doped with second type dopants, a second well region doped with first type dopants, and a third well region. The transistor also includes a first isolation structure neighboring the first well region, a second isolation structure neighboring the the second well region and the third well region, a drain region doped with the first type dopants disposed in the third well region, a source region doped with the first type dopants disposed in the first well region, and a gate disposed at least partially over the second isolation structure. The transistor can be configured as a depletion mode transistor.

The invention relates to a DEPFET comprising: a semiconductor substrate (100) of a first conduction type, which has a first main surface (101) and a second main surface (102), which are opposite one another; a source terminal region (1s) of a second conduction type on the first main surface (101); a drain terminal region (1d) of a second conduction type; a channel region (10), which is arranged between the source terminal region (1s) and the drain terminal region (1d); a gate electrode (11), which is separated from the channel region (10) by a gate insulator (6); a rear activation region (104) of a second conduction type, which is formed on the second main surface (102); and a substrate doping increase region (2) of a first conduction type, which is formed at least under the source terminal region (1s) and under the channel region (10), the substrate doping increase region (2) having a signal charge control region (20) of the first conduction type below the gate electrode (11), in which signal charge control region the effective doping dose has a higher value than at other points of the substrate doping increase region (2) below the gate electrode.

The present application relates to a semiconductor die, comprising a silicon carbide (SiC) semiconductor body comprising a first doping type region; a metallization on a first side of the SiC semiconductor body; an inorganic passivation layer system; a lateral edge of the inorganic passivation layer system arranged on the SiC semiconductor body, wherein the lateral edge of the inorganic passivation layer system is laterally offset inwards from a lateral edge of the SiC semiconductor body, the SiC semiconductor body being uncovered by the inorganic passivation layer system in an edge area, wherein a second doping type well is formed at the first side of the SiC semiconductor body in the first doping type region, the second doping type well extending from below the inorganic passivation layer system into the edge area.

In a disclosed Schmitt trigger, an input stage includes a first p-channel field effect transistor (PFET) and a second PFET, which are connected in series to a VDD rail, and a first n-channel field effect transistor (NFET) and a second NFET, which are connected in series between ground and the second PFET. An output stage includes additional FETs for hysteresis. The first PFET and first NFET are different from the other FETs and have a higher voltage rating. For example, the first PFET and first NFET can be buried oxide field effect transistors (BOXFETs) and the other FETs can be laterally diffused metal oxide semiconductor field effect transistors (LDMOSFETs)). Gates of the first PFET and first NFET are connected to an input node. Gates of the second PFET and NFET are connected to receive reference voltages to prevent safe operating area (SOA) violations and control trigger voltage levels.

A channel stop and well dopant migration control implant (e.g., of argon) can be used in the fabrication of a transistor (e.g., PMOS), either around the time of threshold voltage adjust and well implants prior to gate formation, or as a through-gate implant around the time of source/drain extension implants. With its implant depth targeted about at or less than the peak of the concentration of the dopant used for well and channel stop implants (e.g., phosphorus) and away from the substrate surface, the migration control implant suppresses the diffusion of the well and channel stop dopant to the surface region, a more retrograde concentration profile is achieved, and inter-transistor threshold voltage mismatch is improved without other side effects. A compensating through-gate threshold voltage adjust implant (e.g., of arsenic) or a threshold voltage adjust implant of increased dose can increase the magnitude of the threshold voltage to a desired level.

A partially depleted silicon-on-insulator (PDSOI) transistor and a method for fabricating the PDSOI transistor are disclosed. The PDSOI transistor includes: an SOI substrate including a bottom silicon layer, a buried oxide layer formed on the bottom silicon layer and a top silicon layer formed on the buried oxide layer, the top silicon layer formed therein with a well region; a gate structure formed on the SOI substrate; and a source and a drain, which are located in the well region on opposite sides of the gate structure. The source is formed by epitaxy, and at least a portion of the source is of the same conductivity type as the well region.

A partially depleted silicon-on-insulator (PDSOI) transistor and a method for fabricating the PDSOI transistor are disclosed. In PDSOI transistor, a first space is provided between a bottom surface of a source and a top surface of a buried oxide layer, and a second space is provided between a bottom surface of a drain and the top surface of the buried oxide layer. Moreover, a source contact structure extends into the source and a third space is provided between the source contact structure and the top surface of the buried oxide layer. With this configuration, electric charge can be picked up from the body region through the third space and the source contact structure, thereby avoiding the problem of the floating body effect (FBE) and enabling the PDSOI transistor to have improved quality and reliability.

Provided is a semiconductor device, including a gate trench between a source region and a drain region on a substrate, a first gate insulating layer covering a lower surface and a sidewall of the gate trench, a second insulating layer in contact with an upper region of a sidewall of the first gate insulating layer in the gate trench, and a gate electrode in the gate trench, the gate electrode including a lower buried portion in contact with the first gate insulating layer, wherein the lower buried portion is in a lower region of the gate trench, and an upper buried portion is on the lower buried portion in an upper region of the gate trench, in which the lower buried portion includes a first conductive layer in contact with a sidewall surface and a lower region of the first gate insulating layer, the upper buried portion includes a work function adjustment layer on the second insulating layer, and a second conductive layer in the upper region of the gate trench, wherein the second conductive layer is in contact with the work function adjustment layer and the first conductive layer, and the second conductive layer includes a transition metal.

The present disclosure relates to semiconductor structures and, more particularly, to a multi-channel replacement metal gate device and methods of manufacture. The structure includes: a fully depleted semiconductor on insulator substrate; a plurality of fin structures over the fully depleted semiconductor on insulator substrate; and a metal gate structure spanning over the plurality of fin structures and the fully depleted semiconductor on insulator substrate.