A semiconductor device includes: a depletion-type field-effect transistor including a gate terminal, a drain terminal and a source terminal; a group III-V heterojunction bipolar transistor including a base terminal, an emitter terminal electrically connected to the gate terminal and a collector terminal connected to same potential as that of the source terminal; a first resistor connected between the base terminal and the emitter terminal; and a second resistor connected between the base terminal and the collector terminal.

An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provided and an electrically conductive contact extends within the insulating multilayer to emerge onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.

Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced V.sub.T compared to conventional bulk CMOS and can allow the threshold voltage V.sub.T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor.

A fully depleted field effect transistor (FET) and an anti-fuse structure are provided on a same chip. The fully depleted FET and the anti-fuse structure share a same high dielectric (k) constant dielectric material. The anti-fuse structure contains a faceted epitaxial doped semiconductor material as a bottom electrode, a high k dielectric material portion, and a gate electrode material portion as a top electrode. The sharp corners of the faceted epitaxial doped semiconductor material cause electric field concentration, which aid in the reduction of the breakdown voltage of the anti-fuse structure.

A driver IC includes a ring-shaped termination area, and a first area and a second area that are respectively arranged outside and inside the termination area on a layout. A sense MOS that is arranged between floating terminal and a first sense node and is driven at a power supply voltage is formed in the termination area. A fault detection circuit that detects presence of a fault when a voltage of the first sense node is higher than a decision voltage that has been deteLutined in advance in a period of time that a low side driver is driving a low side transistor into an ON state is formed in the first area.

A method of manufacturing a semiconductor device with a fuse is provided including the steps of providing a semiconductor-on-insulator (SOI) structure including an insulating layer and a semiconductor layer formed on the insulating layer, forming a first raised semiconductor region on the semiconductor layer and a second raised semiconductor region on the semiconductor layer adjacent to the first semiconductor region, and performing a silicidation process of the first and second raised semiconductor regions to form a first at least partially silicided raised semiconductor region with a first silicided portion and a second at least partially silicided raised semiconductor region with a second silicided portion.

An aspect of the invention is directed to a silicon-on-insulator device including a silicon layer on an insulating layer on a substrate; a raised source and a raised drain on the silicon layer; a gate between the raised source and the raised drain; a first spacer separating the gate from the raised source and substantially covering a first sidewall of the gate; a second spacer separating the gate from the raised drain and substantially covering a second sidewall of the gate; and a low-k layer over the raised source, the raised drain, the gate and each of the first spacer and the second spacer; and a dielectric layer over the low-k layer.

The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.

An integrated circuit product is disclosed including an SOI structure including a bulk semiconductor substrate, a buried insulation layer positioned on the bulk semiconductor substrate and a semiconductor layer positioned on the insulation layer, wherein, in a first region of the SOI structure, the semiconductor layer and the buried insulation layer are removed and, in a second region of the SOI structure, the semiconductor layer and the buried insulation layer are present above the bulk semiconductor substrate. The product further includes a semiconductor bulk device comprising a first gate structure positioned on the bulk semiconductor substrate in the first region and an SOI semiconductor device comprising a second gate structure positioned on the semiconductor layer in the second region, wherein the first and second gate structures have a final gate height substantially extending to a common height level above an upper surface of the bulk semiconductor substrate.