A semiconductor device, comprising a first semiconductor portion having a first end, a second end, and a slit portion, wherein the width of the slit portion is less than the width of at least one of the first end and the second end; a second portion that is a different material than the first semiconductor portion, a third portion that is a different material than the first semiconductor portion, wherein the second and third portions are on opposite sides of the slit portion, and at least three terminals selected from a group consisting of a first terminal connected to the first end, a second terminal connected to the second end, a third terminal connected to the second portion, and a fourth terminal connected to the third portion.

A method comprises forming a first set of one or more fins in a first region from an insulated substrate and a second set of one or more fins in a second region from the insulated substrate. The insulated substrate comprises a silicon substrate, and an insulator layer deposited on the silicon substrate. The first region comprises a first material layer and the second region comprises a second material layer.

An electrostatic discharge protection device and a method of making the same. The device includes a device area located on a semiconductor substrate. The device also includes an array of coextensive, laterally spaced fingers located within the device area. Each finger includes an elongate source and an elongate drain separated by an elongate gate. The fingers are electrically connected in parallel for conducting an electrostatic discharge current during an electrostatic discharge event. The device further includes a plurality of body contact regions. A layout of the body contact regions is graded such that a greater number of the body contact regions, larger body contact regions, or both are located towards a periphery of the device area than towards a central part of the device area. The layout of the body contact regions may encourage triggering of the electrostatic discharge protection device within the central part of the device area.

A FinFET structure layout includes a semiconductor substrate comprising a plurality of FinFET active areas, and a plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a gate having a gate length parallel to the semiconductor substrate and perpendicular to length of the plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a plurality of metal features connecting a source region or a drain region of a portion of the plurality of FinFET active areas to a plurality of contacts. The plurality of metal features includes a plurality of metal lines parallel to a FinFET channel direction and a plurality of metal lines parallel to a FinFET channel width direction.

An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a first doped region formed in the drain region. The source region and the drain region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The first doped region is electrically connected to a ground potential.

A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

A semiconductor device includes a channel region of a first conductivity type, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film, a first region of a second conductivity type and a second region of the second conductivity type, which are formed along the gate electrode while facing each other with the gate electrode interposed between the first region and the second region, a semiconductor region of the second conductivity type on which the first region, the second region and the channel region are formed, and an element isolation region which surrounds the semiconductor region. The gate electrode extends beyond a boundary portion between the channel region and the element isolation region. A width of the first region is smaller than a width of the second region in a channel width direction of the first region and the second region.

A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first vertical bar structure that includes a first sidewall and a second sidewall disposed over the substrate; a gate disposed along the first sidewall of the first vertical bar structure; a second vertical bar structure electrically coupled to the first vertical bar structure; and a second source/drain feature disposed over the first vertical bar structure; and a p-type FET that includes; a third source/drain feature disposed in the substrate; a third vertical bar structure that includes a third sidewall and a fourth sidewall disposed over the substrate; the gate disposed along the third sidewall of the third vertical bar structure; a fourth vertical bar structure electrically coupled to the third vertical bar structure; and a fourth source/drain feature disposed over the third vertical bar structure.

A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a high-voltage doped region having the first conductivity type and disposed in the high-voltage well, a drain region disposed in the high-voltage well and spaced apart from the high-voltage doped region, a source region disposed in the high-voltage doped region, a first gate structure disposed above a first side portion of the high-voltage doped region between the source region and the drain region, and a second gate structure disposed above a second and opposite side portion of the high-voltage doped region.

A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.