A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.

A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region.

The present invention relates to the field of manufacturing technologies of semiconductor power devices, and more particularly to a method for manufacturing a split-gate power device. In the method for manufacturing a split-gate power device according to the present invention, lateral etching is added to form lateral recesses of a control gate groove below a first insulating film in a process of forming the control gate groove by etching, and therefore, after a first conductive film is deposited, the first conductive film can be directly etched by using the first insulating film as a mask to form control gates. The technical process of the present invention is simplified, reliable and easy to control, and can greatly improve the yield of the split-gate power device. The present invention is particularly suitable for the manufacture of 25V-200V semiconductor power devices.

A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions disposed in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.

A semiconductor device includes a substrate; a first well region disposed in the substrate and with a first electrical property; a second well region with the first electrical property disposed in the substrate and separated from the first well region; a first gate dielectric layer disposed on the first well region and having a first thickness; a second gate dielectric layer, disposed on the second well region, separated from the first gate dielectric layer and having a second thickness less than the first thickness; a first gate electrode disposed on the first gate dielectric layer; a second gate electrode disposed on the second gate dielectric layer and separated from the first gate electrode; a drain region disposed in the first well region; and a source region disposed in the second well region.

An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.

A semiconductor device structure and methods of forming the same are described. The structure includes a first gate structure disposed over a substrate in an active device region, an insulating material disposed over the substrate in a passive device region, a resistor structure disposed over the insulating material in the passive device region, a first conductive contact electrically connected to the resistor structure, a second conductive contact disposed over the resistor structure, and a dielectric layer in contact with the second conductive contact and the resistor structure.

A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

A semiconductor device includes a substrate with first conductivity type and an epitaxial layer; a first trench and a second trench in the epitaxial layer, the depth of the first trench being greater than that of the second trench; a first gate structure including a first gate in the first trench and a first gate dielectric layer; a second gate structure including a second gate in the second trench and a second gate dielectric layer between the second gate and the epitaxial layer; a body region with second conductivity type being spaced apart from the first gate dielectric layer and being contiguous with the second gate dielectric layer; a first electrode region having first conductivity type; a third gate structure on the epitaxial layer and partially overlapping with the body region; and a second electrode. The Avalanche Energy, Single Pulse (EAS) durability of the semiconductor device is improved.

A semiconductor device includes a substrate of first conductive type and an epitaxial layer; a first trench in the epitaxial layer; a first gate electrode structure in the first trench; a body region and the doped region of second conductivity type in the epitaxial layer, the body region is spaced apart from the first gate dielectric layer of the first gate electrode structure, the doped region is separated from the body region by the epitaxial layer and is contiguous with the first gate dielectric layer; a first electrode region of first conductivity type in the body region; a third gate structure on a top surface of the epitaxial layer, including a third gate and a third gate dielectric layer, the third gate structure partially overlaps the first gate dielectric layer and partially overlaps the body region; and a second electrode.