The disclosure relates to a type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins.

A semiconductor device that includes a first conductor (233a1), a second conductor (231), a first transistor (201) over a first insulator, and a second insulator (282) over the first insulator is provided. The first transistor includes a third conductor (242a) and a fourth conductor (242b) that are each electrically connected to a first metal oxide (230), a third insulator (253, 254) over the first metal oxide, and a fifth conductor (260) over the third insulator. The fourth conductor includes a second layer over a first layer. The top surface of the fifth conductor includes a region in contact with the second insulator. The first conductor includes a portion positioned inside an opening of the first insulator, a region in contact with a side surface of the third conductor, and a portion positioned inside an opening of the second insulator. The second conductor includes a region in contact with the second layer and a portion positioned inside an opening of the second insulator. The top surface of the first conductor and the top surface of the second conductor are level with each other.

A three-dimensional structure with an FD-SOI transistor includes a handler wafer, a first device layer and a second device layer stacked in sequence from bottom to top. The first device layer includes a first SOI layer, a first FD-SOI transistor and a first back gate. The first SOI layer includes a first front side and a first back side. The first FD-SOI transistor is disposed on the first front side. The first back gate is disposed on the first back side. The second device layer includes a second SOI layer, a second FD-SOI transistor and a second back gate. The second SOI layer includes a second front side and a second back side. The second FD-SOI transistor is disposed on the second front side. The second back gate is disposed on the second back side.

A semiconductor device is provided. The semiconductor device includes a substrate, a first gate electrode, and a second gate electrode. The first gate electrode is disposed on the substrate. The first gate electrode has a first dopant of a first conductive type. The second gate electrode is disposed on the substrate. The second gate electrode has a second dopant of a second conductive type different from the first conductive type.

A semiconductor device includes a substrate, a first active structure, a conductive portion and a first helmet. The first active structure is formed on the substrate and includes a plurality of first active channel sheets and a plurality of first metal gate structures vertically stacked to each other, wherein the topmost first metal gate structure includes a first inner spacer. The conductive portion is connected with the topmost first active channel sheet. The first helmet is formed above the first inner spacer and covers a lateral surface of the conductive portion.

The present disclosure relates to a universal logic memory cell composed of triple-gate silicon devices. The universal logic memory cell according to one embodiment of the present disclosure may perform a ternary logic operation function and a memory function using triple-gate silicon devices driven by a positive feedback loop.

High voltage isolation devices for semiconductor devices and associated systems, are disclosed herein. The isolation device may support operations of a 3-dimensional NAND memory array of the semiconductor device. In some embodiments, during high voltage operations (e.g., erase operations), the isolation device may provide a high voltage to the memory array while isolating other circuitry supporting low voltage operations of the memory array from the high voltage. The isolation device may include a set of narrow active areas separating the low voltage circuitry from the high voltage and a gate over the narrow active areas. In a further embodiment, the isolation device includes interdigitated narrow active areas and a common gate over the interdigitated narrow active areas to reduce an area occupied by the isolation devices.

A semiconductor device includes a semiconductor body having first and second opposing surfaces in a vertical direction, and transistor cells at least partly integrated in the semiconductor body. Each transistor cell includes first and second source regions, first and second body regions, a drift region separated from the respective source region by the corresponding body region, a first gate electrode, and a control electrode. The drift region is arranged between the first and the second body region in a horizontal direction that is perpendicular to the vertical direction and extends from the first surface into the semiconductor body in the vertical direction. The first gate electrode is configured to provide a control signal for switching the transistor cell. The control electrode is configured to provide a control signal for controlling a JFET formed by the first body region, the drift region, and the second body region.

A structure including a first emitter-collector (E/C) layer over a substrate. The structure further includes an intrinsic base layer over the first E/C layer and a second E/C layer over the intrinsic base layer. The structure includes an extrinsic base layer on the intrinsic base layer and adjacent the second E/C layer. The structure includes a gate structure on the intrinsic base layer and overhanging a lateral sidewall of the intrinsic base.