A semiconductor device fabricated by forming FET fins from a layered semiconductor structure. The layered semiconductor structure incudes a sacrificial layer. Further by forming dummy gate structures on the FET fins, recessing the FET fins between dummy gate structures, growing source-drain regions between FET fins and the sacrificial layer, replacing active region dummy gate structures with high-k metal gates structures, and replacing the sacrificial layer with a dielectric isolation material, wherein the dielectric isolation material extends across the active region.

An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium.

In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium.

Method and structure for enhancing channel performance in a vertical gate all-around device, which provides a device comprising: a source region; a drain region aligned substantially vertically to the source region; a channel structure bridging between the source region and the drain region and defining a substantially vertical channel direction; and a gate structure arranged vertically between the source region and the drain region and surrounding the channel structure. The channel structure comprises a plurality of channels extending substantially vertically abreast each other, each bridging the source region and the drain region, and at least one stressor interposed between each pair of adjacent channels and extending substantially along the vertical channel direction; the stressor affects lateral strain on the adjacent channels, thereby straining the channels in the vertical channel direction.

The present disclosure generally relate to methods for forming an epitaxial layer on a semiconductor device, including a method of forming a tensile-stressed germanium arsenic layer. The method includes heating a substrate disposed within a processing chamber, wherein the substrate comprises silicon, and exposing a surface of the substrate to a germanium-containing gas and an arsenic-containing gas to form a germanium arsenic alloy having an arsenic concentration of 4.510.sup.20 atoms per cubic centimeter or greater on the surface.

A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.

Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs.

Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs.

A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.