First and second transistors with different electrical characteristics are supported by a substrate having a first-type dopant. The first transistor includes a well region within the substrate having the first-type dopant, a first body region within the well region having a second-type dopant and a first source region within the first body region and laterally offset from the well region by a first channel. The second transistor includes a second body region within the semiconductor substrate layer having the second-type dopant and a second source region within the second body region and laterally offset from material of the substrate by a second channel having a length greater than the length of the first channel. A gate region extends over portions of the first and second body regions for the first and second channels, respectively.

A method for integrating a vertical transistor and a three-dimensional channel transistor includes forming narrow fins and wide fins in a substrate; forming a first source/drain (S/D) region at a base of the narrow fin and forming a gate dielectric layer and a gate conductor layer over the narrow fin and the wide fin. The gate conductor layer and the gate dielectric layer are patterned to form a vertical gate structure and a three-dimensional (3D) gate structure. Gate spacers are formed over sidewalls of the gate structures. A planarizing layer is deposited over the vertical gate structure and the 3D gate structure. A top portion of the narrow fin is exposed. S/D regions are formed on opposite sides of the 3D gate structure to form a 3D transistor, and a second S/D region is formed on the top portion of the narrow fin to form a vertical transistor.

A power conversion device including a low-side MOSFET, a high-side MOSFET and an integrated control IC chip is disclosed. The power conversion device further includes a substrate comprising a first mounting area having a first group of welding discs and a second mounting area having a second group of welding discs; a first chip flipped and attached to the first mounting area; a second chip flipped and attached to the second mounting area; a metal clip; and a molding body covering a front surface of the substrate, the first chip, the second chip and the metal clip. Metal pads on a front side of the first chip is attached to the first group of welding discs. Metal pads on a front side of the second chip is attached to the second group of welding discs. The metal clip connects a connection pad to a back metal layer of the first chip.

A method for producing a semiconductor device includes depositing an oxide film containing an impurity having a first conductivity type on a substrate. A nitride film and an oxide film containing an impurity having a second conductivity type different from the first conductivity type are deposited. The oxide film having the first conductivity type, the nitride film, and the oxide film having the second conductivity type are etched to form a contact hole. Epitaxial growth is performed in the contact hole to form a pillar-shaped silicon layer. The nitride film is removed and a metal is deposited to form an output terminal.

A semiconductor device includes a third first-conductivity-type semiconductor layer on a semiconductor substrate, and a first pillar-shaped semiconductor layer on the semiconductor substrate. The first pillar-shaped semiconductor layer including a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, a second second-conductivity-type semiconductor layer, and a third second-conductivity-type semiconductor layer. A first gate insulating film is around the first body region, and a first gate is around the first gate insulating film. A second gate insulating film is around the second body region and a second gate is around the second gate insulating film. An output terminal is connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer, and a first contact connects the first gate and the second gate.

A power MOSFET or a power rectifier may be fabricated according to the invention to include a gate trench and a field plate trench. Both trenches can be formed with a two-step etching process as described in detail in the specification. The devices that embody this invention can be fabricated with higher packaging density and better and more tightly distributed device parameters such as the V.sub.F, R.sub.DSS, and BV.

The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

A static random access memory (SRAM) cell includes first through fourth source diffusion regions sequentially arranged in a first direction, a first pass-gate transistor, a source region of which is formed by the first source diffusion region, first and second pull-up transistors, source regions of which are formed by the second source diffusion region, first and second pull-down transistors, source regions of which are formed by the third source diffusion region, a second pass-gate transistor, a source region of which is formed by the fourth source diffusion region, and an intermediate region between the first and second pass-gate transistors linearly extending along a direction parallel to the first direction and across the entire SRAM cell. Each of the first source diffusion region and the fourth source diffusion region is spaced-apart from the intermediate region.

Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer formed thereon and of the opposite conductivity type, and a first epitaxial layer formed on mesas of the second semiconductor layer. An electric field along a length of the first epitaxial layer is uniformly distributed.

A method for producing a semiconductor device includes forming a fin-shaped semiconductor layer on a substrate, forming a first insulating film around the fin-shaped semiconductor layer, and a first metal film is formed around the first insulating film. A pillar-shaped semiconductor layer is formed on the fin-shaped semiconductor layer and a gate insulating film is formed around the pillar-shaped semiconductor layer. A gate electrode is formed around the gate insulating film, the gate electrode being made of a third metal, and a gate line is connected to the gate electrode. A second insulating film is formed around a sidewall of an upper portion of the pillar-shaped semiconductor layer, and a second metal film is formed around the second insulating film.