A semiconductor device of embodiments includes: a silicon carbide layer having a first face and a second face and including a first trench, a second trench having a distance of 100 nm or less from the first trench, a first silicon carbide region of n-type, a second silicon carbide region of p-type between the first trench and the second trench, a third silicon carbide region of n-type between the second silicon carbide region and the first face, a fourth silicon carbide region between the first trench and the second silicon carbide region and containing oxygen, and a fifth silicon carbide region between the second trench and the second silicon carbide region and containing oxygen; a first gate electrode in the first trench; a second gate electrode in the second trench; a first gate insulating layer; a second gate insulating layer; a first electrode; and a second electrode.

A process of forming a gate insulating film in a silicon carbide semiconductor device. The process includes performing a first stage of a nitriding heat treatment by a gas containing oxygen and nitrogen, followed by depositing an oxide film, and then performing a second stage of the nitriding heat treatment by a gas containing nitric oxide and nitrogen. The amount of nitrogen at the treatment starting point of the first stage of the nitriding heat treatment is greater than the amount of nitrogen at the treatment starting point of the second stage of the nitriding heat treatment. The amount of nitrogen at the treatment ending point of the second stage of the nitriding heat treatment is greater than the amount of nitrogen at the treatment ending point of the first stage of the nitriding heat treatment.

A transistor device and a method for manufacturing a transistor device are disclosed. The transistor device includes a semiconductor body and a plurality of transistor cells. Each transistor cell includes: a drift region, a body region, and a source region; a gate electrode connected to a gate node; and a field electrode connected to a source node. The gate electrode is dielectrically insulated from the body region by a gate dielectric, and is arranged in a first trench extending from a first surface into the semiconductor body. The field electrode is dielectrically insulated from the drift region by a high-k dielectric, and is arranged in a second trench. The second trench extends from the first surface into the semiconductor body and is spaced apart from the first trench, and the field electrode extends at least as deep as the first trench into the semiconductor body.

A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the semiconductor layer. A first contact wiring is formed on a back surface portion of the semiconductor layer, and defines one electrode electrically connected to the transistor element. The first contact wiring has a first wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a second wiring layer formed on the first wiring layer and having a resistivity lower than that of the first wiring layer.

A multi-level gate driver applied to the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) includes three parts: the SiC MOSFET information detection circuit, the signal level shifting circuit, and the segmented driving circuit. The SiC MOSFET information detection circuit includes the SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit. The segmented driving circuit includes a turn-on segmented driving circuit and a turn-off segmented driving circuit. The SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit process a drain-source voltage and a drain-source current during the SiC MOSFET's switching as enable signals for segmented driving; the signal level shifting circuit transfers enable signals required by the segmented driving circuit to the suitable power supply rail; and the SiC MOSFET turn-on segmented driving circuit and the turn-off segmented driving circuit select suitable driving currents.

An embodiment semiconductor device includes a conductive region extending in a first direction and a second direction intersecting the first direction and stacked in a third direction intersecting the first direction and the second direction and a termination region at an end of the conductive region in the first direction, wherein the termination region includes an n+ type substrate, an n type layer disposed on an upper surface of the n+ type substrate and having a plurality of first trenches opening upward in the third direction, and a lower gate runner covering the plurality of first trenches and disposed on an upper surface of the n type layer.

An embodiment semiconductor device includes an N type layer having a trench therein, a P type region within the N type layer, an N+ type region within the P type region, a gate electrode within the trench including a first gate electrode having an upper surface lower than an upper surface of the P type region and a second gate electrode having an upper surface lower than the upper surface of the first gate electrode, and source and drain electrodes insulated from the gate electrode, wherein the N+ type region includes a first N+ type region on a side of the first gate electrode and having a lower surface lower than the upper surface of the first gate electrode and a second N+ type region on a side of the second gate electrode and having a lower surface lower than the lower surface of the first N+ type region.

A silicon carbide semiconductor device being capable of operating at least 100 degree C., includes a semiconductor substrate having an active region, the semiconductor substrate having first and second surfaces opposite to each other, a first semiconductor region of an n type, provided in the semiconductor substrate, a second semiconductor region of a p type, provided in the active region, between the first surface of the semiconductor substrate and the first semiconductor region, and a device element structure including a pn junction between the second and first semiconductor regions that forms a body diode through which a current flows when the semiconductor device is turned on. A stacking fault area that is a sum of areas that contain stacking faults within an entire active region of the first surface of the semiconductor substrate in the first surface is set to be greater, the higher a breakdown voltage is set.

A silicon carbide semiconductor power transistor and a method of manufacturing the same. The silicon carbide semiconductor power transistor of the disclosure includes a substrate made of silicon carbide (SiC), a drift layer disposed on the substrate, a gate layer formed on the drift layer, a plurality of first and second well pick-up regions disposed in the drift layer, a plurality of source electrodes, and a plurality of contacts. A plurality of V-grooves is formed in the drift layer. A first opening is formed in the gate layer at a bottom of each of the V-grooves, and a second opening is formed in the gate layer at a top of the drift layer between the V-grooves. The plurality of contacts is disposed inside the second opening to be in direct contact with the second well pick-up regions.

An object is to provide a technique that enhances the reliability of a silicon carbide semiconductor device without impairing the productivity of the silicon carbide semiconductor device. In a semiconductor structure, an active region and a terminal region connected to the active region along the outer periphery of the active region are defined, a silicon carbide substrate includes a high resistance region provided in the termination region, or provided in the termination region and a portion of the active region that is in contact with the termination region, and in contact with the buffer layer, and resistance of the high resistance region is higher than resistance of a remaining region of the silicon carbide substrate other than the high resistance region.