In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.

A p-type base region, n.sup.+-type source region, p.sup.+-type contact region, and n-type JFET region are formed on a front surface side of a silicon carbide base by ion implantation. The front surface of the silicon carbide base is thermally oxidized, forming a thermal oxide film. Activation annealing at a high temperature of 1500 degrees C. or higher is performed with the front surface of the silicon carbide base being covered by the thermal oxide film. The activation annealing is performed in a gas atmosphere that includes oxygen at a partial pressure from 0.01 atm to 1 atm and therefore, the thermal oxide film thickness may be maintained or increased without a decrease thereof. The thermal oxide film is used as a gate insulating film and thereafter, a poly-silicon layer that is to become a gate electrode is deposited on the thermal oxide film, forming a MOS gate structure.

An insulated gate silicon carbide semiconductor device includes: a drift layer of a first conductivity type on a silicon carbide substrate of 4H type with a {0001} plane having an off-angle of more than 0 as a main surface; a first base region; a source region; a trench; a gate insulating film; a protective diffusion layer; and a second base region. The trench sidewall surface in contact with the second base region is a surface having a trench off-angle of more than 0 in a <0001> direction with respect to a plane parallel to the <0001> direction. The insulated gate silicon carbide semiconductor device can relieve an electric field of a gate insulating film and suppress an increase in on-resistance and provide a method for manufacturing the same.

A silicon carbide semiconductor device includes a silicon carbide layer having a first main surface and a second main surface opposite to the first main surface. In the second main surface of the silicon carbide layer, a trench having a depth in a direction from the second main surface toward the first main surface is provided, and the trench has a sidewall portion where a second layer and a third layer are exposed and a bottom portion, where a first layer is exposed. A position of the bottom portion of the trench in a direction of depth of the trench is located on a side of the second main surface relative to a site located closest to the first main surface in a region where the second layer and the first layer are in contact with each other, or located as deep as the site in the direction of depth.

A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

A MOS gate structure is provided on a p-type base layer side of a silicon carbide semiconductor base formed by sequentially forming on a front surface of an n.sup.+-type silicon carbide substrate, an n-type drift layer and a p-type base layer by epitaxial growth. On the base front surface, in an edge termination structure region, a step portion occurring between the p-type base layer and the n-type drift layer, and a flat portion farther outward than the step portion are provided. In a surface layer of the n-type drift layer, a p.sup.+-type base region constituting the MOS gate structure is provided so as to contact the p-type base layer. The outermost p.sup.+-type base region extends from an active region into the flat portion and the entire lower side of this portion is covered by an innermost p.sup.-type region constituting an edge termination structure provided in the flat portion.

A semiconductor device includes first, second, third, and fourth electrodes, a first insulating film, and first, second third, and fourth silicon carbide layers. A first distance between the first electrode and a first interface between the fourth electrode and fourth silicon carbide region is longer than a second distance between the first insulating film and a second interface between the third silicon carbide region and the fourth silicon carbide region. The fourth silicon carbide region is between the third silicon carbide region and the second silicon carbide region in a direction perendicular to the second interface.

A semiconductor device according to an embodiment includes a SiC layer having a first plane and a second plane, a gate insulating film provided on the first plane, a gate electrode provided on the gate insulating film, a first SiC region of a first conductivity type provided in the SiC layer, a second SiC region of a second conductivity type provided in the first SiC region, a third SiC region of the first conductivity type provided in the second SiC region, and a fourth SiC region of the first conductivity type provided between the second SiC region and the gate insulating film, the fourth SiC region interposed between the second SiC regions, and the fourth SiC region provided between the first SiC region and the third SiC region.

In one general aspect, an apparatus can include a silicon carbide (SiC) device can include a gate dielectric, a first doped region having a first conductivity type, a source, a body region of the first conductivity type, and a second doped region having a second conductivity type. The second doped region can have a first portion and a second portion. The first portion can be disposed between the first doped region and the body region and the second portion can be disposed between the first doped region and the gate dielectric. The first portion of the second doped region can have a width less than a width of the first doped region.

A power semiconductor device includes a silicon carbide substrate and at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The device further comprising an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts.