Disclosed herein is a shielded-gate silicon carbide trench MOS-controlled switch, such as a MOSFET or IGBT, with a reduced Miller capacitance. The switch disclosed herein can be used in a variety of applications, including high temperature and/or high voltage power conversion.

The present disclosure relates to a power module that has a housing with an interior chamber and a plurality of switch modules interconnected to facilitate switching power to a load. Each of the plurality of switch modules comprises at least one transistor and at least one diode mounted within the interior chamber and both the at least one transistor and the at least one diode are majority carrier devices, are formed of a wide bandgap material system, or both. The switching modules may be arranged in virtually any fashion depending on the application. For example, the switching modules may be arranged in a six-pack, full H-bridge, half H-bridge, single switch or the like.

A silicon carbide vertical MOSFET includes an N-counter layer of a first conductivity type formed in a surface layer other than a second semiconductor layer base layer selectively formed in a low concentration layer on a surface of the substrate, a gate electrode layer formed through a gate insulating film in at least a portion of an exposed portion of a surface of a third semiconductor layer of a second conductivity type between a source region of the first conductivity type and the N-counter layer of the first conductivity type, and a source electrode in contact commonly with surfaces of the source region and the third semiconductor layer. Portions of the second conductivity type semiconductor layer are connected with each other in a region beneath the N-counter layer.

High voltage-resistance of a switching device including a p-type region being in contact with a lower end of a bottom-insulating-layer is realized. The switching device includes a bottom-insulating-layer disposed at a bottom in a trench, and a gate electrode disposed on a front surface side of the bottom-insulating-layer. A semiconductor substrate includes a first n-type and p-type regions being in contact with the gate insulating film, a second p-type region being in contact with an end of the bottom-insulating-layer, and a second n-type region separating the second p-type region from the first p-type region. Distance A from a rear-surface-side-end of the first p-type region to a front-surface-side-end of the second p-type region, and distance B from a rear-surface-side-end of the-bottom-insulating layer to a rear-surface-side-end of the second p-type region satisfy A<4B.

A JFET having vertical and horizontal channel elements may be made from a semiconductor material such as silicon carbide using a first mask for multiple implantations to form a horizontal planar JFET region comprising a lower gate, a horizontal channel, and an upper gate, all above a drift region resting on a drain substrate region, such that the gates and horizontal channel are self-aligned with the same outer size and outer shape in plan view. A second mask may be used to create a vertical channel region abutting the horizontal channel region. The horizontal channel and vertical channel may each have multiple layers with varying doping concentrations. Angled implantations may use through the first mask to implant portions of the vertical channel regions. The window of the second mask may partially overlap the horizontal JFET region to insure abutment of the vertical and horizontal channel regions.

A silicon carbide substrate includes a first impurity region, a well region in contact with the first impurity region, and a second impurity region separated from the first impurity region by the well region. A first main surface includes a first region in contact with a channel region, and a second region different from the first region. A silicon-containing material is formed on the second region. A first silicon dioxide region is formed on the first region. A second silicon dioxide region is formed by oxidizing the silicon-containing material. A gate runner is electrically connected to a gate electrode and formed in a position facing the second silicon dioxide region. Consequently, a silicon carbide semiconductor device capable of achieving improved insulation performance between the gate runner and the substrate while the surface roughness of the substrate is suppressed, and a method of manufacturing the same can be provided.

A semiconductor device manufacturing method according to an embodiment includes: forming an n-type SiC layer on a SiC substrate; forming a p-type impurity region at one side of the SiC layer; exposing other side of the SiC layer by removing at least part of the SiC substrate; implanting carbon (C) ions into exposed part of the SiC layer; performing a heat treatment; forming a first electrode on the p-type impurity region; and forming a second electrode on the exposed part of the SiC layer.

A silicon carbide semiconductor device includes a silicon carbide layer 32 of a first conductivity type, a silicon carbide layer 36 of a second conductivity type, a gate trench 20, a gate electrode 79 provided in the gate trench 20, and a protection trench 10 formed to a depth greater than the gate trench 20. A region in the horizontal direction that includes both the gate trench 20 and a protection trench 10 that surrounds the gate trench 20 with at least a part of the gate trench 20 left unenclosed is a cell region, and a region in the horizontal direction that includes a protection trench 10 and in which a gate pad 89 or a lead electrode connected to the gate pad is disposed is a gate region.

A method for manufacturing a semiconductor device, includes: (a) providing a SiC epitaxial substrate in which on a SiC support substrate, a SiC epitaxial growth layer having an impurity concentration equal to or less than 1/10,000 of that of the SiC support substrate and having a thickness of 50 m or more is disposed; (b) forming an impurity region, which forms a semiconductor element, on a first main surface of the SiC epitaxial substrate by selectively injecting impurity ions; (c) forming an ion implantation region, which controls warpage of the SiC epitaxial substrate, on a second main surface of the SiC epitaxial substrate by injecting predetermined ions; and (d) heating the SiC epitaxial substrate after (b) and (c).

After a trench is formed, a deposition film is formed on the front surface of a base material and an inner wall of the trench such that a thickness of a portion of the deposition film covering the front surface of the base material is greater than a thickness of a portion of the deposition film covering the inner wall of the trench. The total thickness of the deposition film is then reduced until the inner wall of the trench is exposed, leaving only the portion of the deposition film covering the front surface of the base material. By performing sacrificial oxidation in this state, the thermal oxide film caused by thermal oxidation barely grows at the interface of the front surface of the base material and the deposition film, and thus the thickness of an n+ source region is mostly maintained.