A semiconductor device is provided, including a semiconductor body having a semiconductor substrate and an epitaxial layer on the substrate, the epitaxial layer being a first conductivity type, and an active area and a termination area adjacent the active area are in the epitaxial layer, the termination area includes a plurality of laterally spaced apart first regions, the first regions being a second conductivity type opposite to the first type, the plurality of first regions enclosing, observed from a top view of the semiconductor device, the active area and one or more second regions, the second regions are in between the plurality of spaced apart first regions, respectively, the one or more second regions extend further into the epitaxial layer than the plurality of first regions, and the one or more second regions include an insulation material for insulating the plurality of first regions from one another.

A semiconductor device comprises a silicon carbide based semiconductor layer structure that comprises an active region. A gate trench is provided in an upper portion of the semiconductor layer structure, the gate trench having a first rounded lower corner and a second rounded lower corner. A gate electrode is provided in the gate trench. Within the active region, an upper surface of the gate electrode is below or coplanar with an upper surface of the semiconductor layer structure.

A semiconductor device has an active region through which a main current flows, a gate ring region surrounding a periphery of the active region, a source ring region surrounding a periphery of the gate ring region, and a termination region surrounding a periphery of the source ring region. The semiconductor device has a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, and further, in the active region, first semiconductor regions of the first conductivity type, a gate insulating film, first gate electrodes, an interlayer insulating film, a first first-electrode, a first plating film, and a second electrode. The semiconductor device has, in the source ring region, a second first-electrode provided at a surface of the second semiconductor layer, and a second plating film provided on the second first-electrode.

A semiconductor device includes an N+ type substrate, an N type layer disposed on a first surface of the N+ type substrate and having a trench opened to a surface opposite to the surface facing the N+ type substrate, a P type region disposed in the N type layer and disposed on a side surface of the trench, a gate electrode disposed in the trench, and a source electrode and a drain electrode insulated from the gate electrode. The N type layer includes a P type shield region covering a bottom surface and an edge of the trench.

A method for producing a power FinFET with two-part control electrodes. The method includes: creating a first structured mask including oxide regions and first and second open regions on the front side of a semiconductor body via lithography; creating first and second trenches below the first and second open regions, respectively, by a first etching process starting from the front side of the semiconductor body into the drift layer, the first and second trenches being arranged substantially parallel to one another and alternate, the second trenches have a smaller width than the first trenches; applying a polysilicon layer onto the front side so that the first and second trenches are filled; applying an isotropic oxide layer onto the front side of the semiconductor body; creating a second structured mask on the isotropic oxide layer via lithography, wherein the second structured mask is open above the first trenches.

A semiconductor device includes a first-conductivity-type drift region provided in a semiconductor substrate; a trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate; a mesa portion provided in contact with the trench portion in an array direction orthogonal to the extending direction; a second-conductivity-type base region provided in the mesa portion above the drift region and in contact with the trench portion; and a second-conductivity-type floating region provided in the mesa portion below the base region, in contact with the trench portion, and provided in at least a part of the mesa portion in the array direction.

A semiconductor device includes an IGBT in an IGBT portion of a semiconductor body and a diode in a diode portion of the semiconductor body. The diode includes an anode region of a first conductivity type and confined by diode trenches along a first lateral direction. Each of the diode trenches includes a diode trench electrode and a diode trench dielectric. A first contact groove extends into the anode region along a vertical direction from the first surface of the semiconductor body. An anode contact region of the first conductivity type adjoins a bottom side of the first contact groove. A cathode contact region of a second conductivity type adjoins a second surface of the semiconductor body opposite to the first surface. The IGBT includes a gate trench including a gate electrode and a gate dielectric, a source region, an emitter electrode, a drift region, and a second contact groove.

According to one embodiment, a semiconductor device includes first and second electrodes, first to fifth semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode, and electrically connected to the first electrode. The second semiconductor region is provided on a part of the first semiconductor region. The third semiconductor region is provided on another part of the first semiconductor region. The third semiconductor region includes first and second regions. The fourth semiconductor region is provided on the second semiconductor region. The fifth semiconductor region is provided on a part of the fourth semiconductor region. The gate electrode faces the fourth semiconductor region with a gate insulating layer interposed between the gate electrode and the fourth semiconductor region. The second electrode is provided on the fourth and fifth semiconductor regions. The second electrode is electrically connected to the fourth and fifth semiconductor regions.

At any timing after formation of gate electrodes, particle beam irradiation is performed to a semiconductor wafer having an n.sup.-type drift region constituted by an n.sup.-type epitaxial layer and having an n-type impurity concentration that is higher than a target majority carrier concentration (design value) of the n.sup.-type drift region. Point defects of a defect density corresponding to an irradiation dose of the particle beam are generated in the n.sup.-type drift region by the particle beam irradiation, whereby an effective majority carrier concentration of the n.sup.-type drift region is adjusted and reduced with respect to the n-type impurity concentration of the n.sup.-type drift region, to approach the design value. After formation of the n.sup.-type epitaxial layer, the n-type impurity concentration of the n.sup.-type drift region may be measured, or the n.sup.-type epitaxial layer may be formed to have an n-type impurity concentration higher than the design value.

A semiconductor device is provided. The semiconductor device includes a first conductive type substrate; a second conductive type body region disposed in the first conductive type substrate, wherein the first conductive type is different from the second conductive type; a first conductive type first well region disposed in the second conductive type body region; a gate structure disposed over the top surface of the first conductive type substrate; a source region, wherein the source region includes a heavily-doped first conductive type source region and is disposed in the second conductive type body region; and a drain region, wherein the drain region is heavily doped first conductive type and is disposed in the first conductive type first well region.