A semiconductor integrated circuit includes a first well region of a first conductivity type; a second well region of a second conductivity type provided in an upper part of the first well region; a current suppression layer of the first conductivity type provided in a lower part of the semiconductor substrate immediately below the first well region, separated from the first well region; and an isolation region of the second conductivity type provided in an upper part of the semiconductor substrate, separated from the first well region, a reference potential being applied to the isolation region. The semiconductor substrate is the second conductivity type.

Trenches and n.sup.+ high impurity concentration regions are formed in a first principal surface side of a silicon carbide semiconductor substrate. In the n.sup.+ high impurity concentration regions, third n-type regions that respectively surround first p.sup.+ base regions contacting a p-type base layer and have a higher impurity concentration than the n.sup.+ high impurity concentration regions, as well as fourth n-type regions that respectively surround second p.sup.+ base regions formed at the bottoms of the trenches and also have a higher impurity concentration than the n.sup.+ high impurity concentration regions, are formed.

A MOS transistor comprises a substrate of a first conductivity, a first region of the first conductivity formed over the substrate, a second region of the first conductivity formed in the first region, a first drain/source region of a second conductivity formed in the second region, a second drain/source region of the second conductivity and a body contact region of the first conductivity, wherein the body contact region and the first drain/source region are formed in an alternating manner from a top view.

A semiconductor device includes a first compound semiconductor material, a second compound semiconductor material on the first compound semiconductor material, the second compound semiconductor material having a first doping concentration and including a different material than the first compound semiconductor material, a control electrode, and at least one buried semiconductor material region having a second doping concentration different from the first doping concentration. The at least one buried semiconductor material region is disposed in the second compound semiconductor material in a region other than a region of the second compound semiconductor material being covered by the control electrode.

A semiconductor device is provided that can prevent a current from being concentrated into a specific chip, and can reduce loss as well as noise. The semiconductor device according to the present invention includes: a switching element; a main diode that is connected in parallel to the switching element; and an auxiliary diode that is connected in parallel to the switching element and has a different structure from that of the main diode, wherein in a conductive state a current flowing through the auxiliary diode is smaller than that through the main diode, and in a transition period from the conductive state to a non-conductive state a current flowing through the auxiliary diode is larger than that through the main diode.

A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.

In a front surface of a semiconductor base body, a gate trench is disposed penetrating an n.sup.+-type source region and a p-type base region to a second n-type drift region. In the second n-type drift region, a p-type semiconductor region is selectively disposed. Between adjacent gate trenches, a contact trench is disposed penetrating the n.sup.+-type source region and the p-type base region, and going through the second n-type drift region to the p-type semiconductor region. A source electrode embedded in the contact trench contacts the p-type semiconductor region at a bottom portion and corner portion of the contact trench, and forms a Schottky junction with the second n-type drift region at a side wall of the contact trench.

A step of forming a silicon carbide substrate includes steps of: forming a first impurity region having a first conductivity type by epitaxial growth; forming an embedded region by performing ion implantation into the first impurity region, the embedded region having a second conductivity type different from the first conductivity type, the embedded region being disposed cyclically; and forming a second impurity region by epitaxial growth, the second impurity region being in contact with the first impurity region and the embedded region, the second impurity region having the second conductivity type, the second impurity region having an impurity concentration lower than an impurity concentration of the embedded region. A trench is formed to have a side portion and a bottom portion. The trench is disposed at the same cycle as the embedded region.

A DMOS transistor integrates a trench Schottky diode into the body contact of the transistor where the body region surrounding the Schottky metal layer forms a guard ring for the Schottky diode.

In a first main surface of a silicon carbide substrate, a second trench having a second side surface which connects to the first main surface and is in contact with a third impurity region and a second impurity region and a second bottom portion continuous to the second side surface is formed. A fourth impurity region has a first region arranged between a second main surface and the second impurity region and a second region connecting the second bottom portion of the second trench and the first region to each other. A first electrode is electrically connected to the third impurity region on a side of the first main surface and is in contact with the second region at the second bottom portion of the second trench.