The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of channel region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed channel region extensions have the same conductivity-type as the channel region and extend outwardly from the channel region and into the JFET region of a first device cell such that a distance between the channel region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to disconnected or connected shielding regions that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a widest portion of the JFET region between adjacent device cells such that a distance between a shielding region and well regions surrounding device cell is less than a parallel JFET width between two adjacent device cells, while maintaining a channel region width and/or a JFET region density that is greater than that of a comparable conventional stripe device. As such, the disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

The subject matter disclosed herein relates to silicon carbide (SiC) power devices. In particular, the present disclosure relates to shielding regions for use in combination with an optimization layer. The disclosed shielding regions reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a portion of the JFET region between adjacent device cells and interrupt the continuity of the optimization layer in a widest portion of the JFET region, where the corners of neighboring device cells meet. The disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

The present invention generally relates to a structure and manufacturing of a power field effect transistor (FET). The present invention provides a planar power metal oxide semiconductor field effect transistor (MOSFET) structure and an insulated gate bipolar transistor (IGBT) structure comprising a split gate and a semi-insulating field plate. The present invention also provides manufacturing methods of the structures.

A source region of a MOSFET includes a source contact region connected to a source electrode, a source extension region adjacent to a channel region of a well region, and a source resistance control region provided between the source extension region and the source contact region. The source resistance control region includes a low concentration source resistance control region which has an impurity concentration lower than that of the source contact region or the source extension region and a high concentration source resistance control region which is formed between the well region and the low concentration source resistance control region and has an impurity concentration higher than that of the low concentration source resistance control region.

A transistor device includes: a first source region and a first drain region spaced apart from each other in a first direction of a semiconductor body; at least two gate regions arranged between the first source region and the first drain region and spaced apart from each other in a second direction of the semiconductor body; at least one drift region adjoining the first source region and electrically coupled to the first drain region; at least one compensation region adjoining the at least one drift region and the at least two gate regions; a MOSFET including a drain node connected to the first source region, a source node connected to the at least two gate region, and a gate node. Active regions of the MOSFET are integrated in the semiconductor body in a device region that is spaced apart from the at least two gate regions.

A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

A semiconductor device includes a first transistor cell of a plurality of transistor cells of a vertical field effect transistor arrangement, and a second transistor cell of the plurality of transistor cells. The first transistor cell and the second transistor cell are electrically connected in parallel. A gate of the first transistor cell and a gate of the second transistor cell are controllable by different gate control signals.

The present invention discloses a method of forming a high voltage junctionless device with drift region. The drift region formed between the semiconductor channel and the dielectric layer enables the high voltage junctionless device to exhibit higher punch-through voltages and high mobility with better performance and reliability.

A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.