A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

A capacitor includes a lower electrode including a perovskite material, an upper electrode spaced apart from the lower electrode, a dielectric layer positioned between the lower electrode and the upper electrode and including a perovskite material, and a passivation layer positioned between the lower electrode and the dielectric layer and including Sr.sub.xTi.sub.yO.sub.3 in which a content of Ti is greater than a content of Sr.

A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.

An integrated chip includes a memory cell within a BEOL metal interconnect. The memory cell may be an FeRAM memory cell. The memory cell is formed over a plurality of openings in a dielectric structure that includes an inter-level dielectric layer. The openings may be form an array or another two-dimensional pattern. The layers of the memory cell line the openings whereby each of a lower electrode layer, a data storage layer, and an upper electrode descend into the openings. The lower electrode layer may pass through an etch stop layer and contact a lower interconnect. There may be a plurality of top electrode vias. The top electrode vias may be offset from the opening. This memory cell structure provides a large area, which leads to low threshold voltages.

Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

The present disclosure relates to an integrated chip including a ferroelectric layer. The ferroelectric layer includes a ferroelectric material. A first relaxation layer including a first material, different from the ferroelectric material, is on a first side of the ferroelectric layer. A second relaxation layer including a second material, different from the ferroelectric material, is on a second side of the ferroelectric layer, opposite the first side. A Young's modulus of the first relaxation layer is less than a Young's modulus of the ferroelectric layer.

A capacitor and a DRAM device, the capacitor including a lower electrode; a dielectric layer structure on the lower electrode, the dielectric layer structure including a first zirconium oxide layer, a hafnium oxide layer, and a second zirconium oxide layer sequentially stacked; and an upper electrode on the dielectric layer structure, wherein the hafnium oxide layer has a tetragonal crystal phase or an orthorhombic crystal phase.

A capacitor device and a semiconductor device including the capacitor device are provided. The capacitor device includes first and second electrodes spaced apart from each other, and a dielectric layer provided between the first electrode and the second electrode. The dielectric layer includes a dielectric material in which ferroelectrics and antiferroelectrics are mixed with each other.

A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.