A field effect transistor (FET) is proposed. The FET includes a transistor cell in a semiconductor substrate having a first surface. The transistor cell includes a source region at the first surface of the semiconductor substrate, a drain region spaced from the source region along a first lateral direction, and a trench gate structure arranged, along the first lateral direction, between the source region and the drain region. The trench gate structure includes a trench gate dielectric and a trench gate electrode. The transistor cell further includes a trench field structure arranged, along the first lateral direction, between the trench gate structure and the drain region. A top side of a first portion of the trench gate electrode is arranged below the first surface at a vertical distance from the first surface.

In a semiconductor device, a semiconductor substrate has an element region and a peripheral region, and trenches are defined on an upper surface of the semiconductor substrate. The trenches extend in a first direction, and are arranged at intervals in a second direction. The element region includes an n-type source region, a p-type contact region, a p-type body region, an n-type drift region, a p-type bottom region, and p-type connection regions. The bottom region is spaced from a bottom surface of the trenches. The connection regions connect the body region and the bottom region, extend in the first direction, and are arranged at intervals in the second direction. The element region has outer side portions and a central portion in the second direction. An interval between the connection regions in the second direction is greater in the outer side portion than in the central portion.

A semiconductor device includes a semiconductor layer, an insulation gate-type first transistor which is formed in the semiconductor layer, an insulation gate-type second transistor which is formed in the semiconductor layer, and a control wiring which is formed on the semiconductor layer such as to be electrically connected to the first transistor and the second transistor, and transmits control signals that control the first transistor and the second transistor to be in ON states in a normal operation and that control the first transistor to be in an OFF state and the second transistor to be in an ON state in an active clamp operation.

A semiconductor device includes a substrate having a first conductivity type, a well region having a second conductivity type and disposed on the substrate, a first trench and a second trench disposed in the well region. In addition, a first field plate and a first dielectric layer surrounding the first field plate are disposed in the first trench. A second field plate and a second dielectric layer surrounding the second field plate are disposed in the second trench. A first gate is disposed above the first field plate. A source electrode is disposed on a first side of the first trench, and a drain electrode is disposed on a second side of the second trench. The source electrode, the first trench, the second trench and the drain electrode are sequentially arranged along a first direction.

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

The present disclosure generally relates to a bird's beak profile of a field oxide region. In an example, a semiconductor device structure includes a semiconductor substrate, a dielectric oxide layer, and a field oxide region. The semiconductor substrate has a top surface. The dielectric oxide layer is over the top surface of the semiconductor substrate. The field oxide region is over the semiconductor substrate. The field oxide region is connected to the dielectric oxide layer through a bird's beak region. A lower surface of the bird's beak region interfaces with the semiconductor substrate. In a cross-section along a direction from the field oxide region to the dielectric oxide layer, the lower surface of the bird's beak region does not have a slope with a magnitude that exceeds 0.57735, where rise of the slope is in a direction normal to the top surface of the semiconductor substrate.

A method of fabricating a semiconductor device includes providing a substrate and forming a well region thereon. First and second trenches are formed in the well region, and a dielectric layer is conformally deposited in these trenches. A conductive layer fills up these trenches and is etched to form a first recess on a first field plate and a second recess on a second field plate. The first and second recesses are filled up with a dielectric material to form first and second dielectric isolation portions. The dielectric layer and the first dielectric isolation portion are etched to form a first groove, and a first gate is formed therein. A source region and a drain region are formed in the well region and located on a side of the first trench and a side of the second trench, respectively.

In an embodiment, a semiconductor device is provided that includes: a vertical power FET configured to switch a load current and provide a channel of a first conductivity type; and a lateral FET configured to drive the vertical power FET and provide a channel of a second conductivity type opposing the first conductivity type. The vertical power FET and the lateral FET are monolithically integrated into a semiconductor substrate of the first conductivity type and a drain of the lateral FET is electrically coupled to a gate of the vertical power FET.

In an embodiment, a semiconductor device includes a vertical power FET for switching a load current, the power FET including a channel region of a first conductivity type and a first lateral FET and a second lateral FET providing an output stage of gate driver circuitry for driving the power FET. The first lateral FET includes a channel region of the first conductivity type and the second lateral FET includes a channel region of a second conductivity type opposing the first conductivity type. The power FET and the first and second lateral FETs are monolithically integrated into a semiconductor substrate of the first conductivity type and that has a first surface. A drain of the first lateral FET and a source of the second lateral FET are electrically coupled to a gate of the power FET.