A non-volatile memory device includes a substrate, a memory cell array on the substrate, a plurality of bonding pads, and a pad circuit. The memory cell array includes a plurality of gate conductive layers stacked on the substrate in a vertical direction and a plurality of channels penetrating into the plurality of gate conductive layers on an upper portion of the substrate. The plurality of bonding pads are on at least part of an upper portion of the memory cell array. The plurality of bonding pads are configured to electrically connect the non-volatile memory device to an external device. The pad circuit is between the substrate and the memory cell array. The pad circuit is electrically connected to at least one of the plurality of bonding pads.

An array substrate and a display panel are provided. The array substrate includes a transparent substrate including a display area and a rim area; a pixel structure and an antistatic switching tube which are arranged on a same side of the transparent substrate. The pixel structure includes a pixel thin-film transistor located in the display area, and the antistatic switching tube is located in the rim area. The pixel structure also includes first grounding wire located on a side of the antistatic switching tube facing away from the transparent substrate, and a second grounding wire located between the antistatic switching tube and the transparent substrate.

A semiconductor device includes a plurality of gate electrodes, and a plurality of stripe contacts, each formed alternately with each of the gate electrodes along a length direction of the gate electrodes. A conductive transistor with a reference potential applied to one of the stripe contacts forming one of a source and a drain is formed. One of the gate electrodes adjacent to one of the stripe contacts forming the other of the source and the drain is used as a first dummy gate electrode. The semiconductor device further includes a metal extending over the first dummy gate electrode to electrically connect together the stripe contacts formed on opposing sides of the first dummy gate electrode, and a pad connected to one of the stripe contacts formed on opposing sides of the first dummy gate electrode, which is provided across the first dummy gate electrode from the conductive transistor.

A semiconductor device and a method of making are disclosed. The device includes a substrate, a power field effect transistor (FET), and integrated sensors including a current sensor, a high current fault sensor, and a temperature sensor. The structure of the power FET includes a drain contact region of a first conductivity type disposed in the substrate, a drain drift region of the first conductivity type disposed over the drain contact region, doped polysilicon trenches disposed in the drain drift region, a body region of a second conductivity type, opposite from the first conductivity type, disposed between the doped polysilicon trenches, a source region disposed on a lateral side of the doped polysilicon trenches and in contact with the body region, and a source contact trench that makes contact with the source region and with the doped polysilicon trenches.

A semiconductor device includes, an anti-fuse element, a transistor connected via the anti-fuse element to a power source terminal which may apply a voltage to the anti-fuse element, an ESD protection element connected to the power source terminal via a node, and a first resistive element disposed in an electric path between the node and the anti-fuse element, wherein resistance of the first resistive element increases with an increase of a voltage applied to the first resistive element.

The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection structures for eFuses. The structure includes an electrostatic discharge (ESD) protection structure operatively coupled to an eFuse, which is structured to prevent unintentional programming of the eFuse due to an ESD event originating at a source.

A power metal oxide semiconductor (MOS) transistor die with a temperature sensing function and an integrated circuit are provided. The power MOS transistor die has a control terminal, a phase terminal, a ground terminal and a temperature signal output terminal, and that further includes a power switch part and a temperature sensing part. The power switch part has: a first electrode coupled to the control terminal; a second electrode coupled to the ground terminal; and a third electrode coupled to the phase terminal. The temperature sensing part has: a first electrode; a second electrode coupled to the temperature signal output terminal; and a third electrode coupled to the third electrode of the power switch part. The power switch part and the temperature sensing part are configured as a MOS transistor made by a same manufacturing process, and are capable of sensing temperature precisely.

A voltage generating circuit comprising: a first switch circuit, operating in a first power domain; a second switch circuit, operating in a second power domain; a first transistor of first type, comprising a control terminal coupled to the first switch circuit and the second first switch circuit, wherein the control terminal of the first transistor of first type is coupled to a predetermined voltage source via the first switch circuit if the first switch circuit is active, wherein the control terminal of the first transistor of first type is coupled to the predetermined voltage source via the second switch circuit if the second switch circuit is active; and an output circuit, coupled to the first transistor of first type and operating in the second power domain.

An electrostatic discharge protection device includes: a substrate of a second conductivity type, the substrate including a well of a first conductivity type; a cathode electrode connected to the substrate; a first diffusion region of the second conductivity type and a second diffusion region of the first conductivity type, formed in the substrate and connected to the cathode electrode; an anode electrode connected to the substrate; a third diffusion region of the second conductivity type and a fourth diffusion region of the first conductivity type, formed in the well and connected to the anode electrode; a fifth diffusion region of the first conductivity type, formed on a border of the substrate and the well; and a sixth diffusion region of the first conductivity type, formed in the substrate between the first and second diffusion regions and the fifth diffusion region and configured to receive a bias voltage from outside.

An electrostatic discharge (ESD) protection device includes a substrate including a plurality of active fins and a plurality of grooves. The ESD protection device includes an insulation layer on the active fins and the grooves, and a gate electrode on the active fins. The ESD protection device includes a first impurity region adjacent to a first side of the gate electrode, and a second impurity region adjacent to a second side of the gate electrode. The second side of the gate electrode may be arranged opposite to the first side. The ESD protection device includes an electrode pattern of a capacitor overlapping the first impurity region, a resistor overlapping the second impurity region, and a connection structure electrically connecting the electrode pattern, the gate electrode, and the resistor to each other.