An integrated circuit includes first to second transistors and a resistive device. The first transistor is coupled between a pad and a first voltage terminal that provides a first supply voltage. The second transistor is coupled in parallel with the first transistor. A breakdown voltage of the first transistor is different from a trigger voltage of the second transistor. The resistive device is coupled between the pad and a second voltage terminal that provides a second supply voltage higher than the first supply voltage, and operates with the second supply voltage in an electrostatic discharge (ESD) event when the first and second transistors discharge a ESD current between the pad and the first voltage terminal.

The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a first source feature, a first drain feature, and a first gate structure. The second transistor includes a second source feature, a second drain feature, and a second gate structure. The first source feature is electrically coupled to the second source feature and the second drain feature is electrically coupled to the first gate structure.

A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.

A display device includes a display panel having a display area and a non-display area, at least one thin-film transistor disposed in the non-display area, at least two or more divided capacitors disposed in the non-display area, and a bridge line for connecting two neighboring divided capacitors with each other among the at least two or more divided capacitors. The non-display area includes a light-blocking film disposed on a substrate and having a stepped first region and a flat second region, and a buffer and gate insulating film disposed on the light-blocking film, and having a bent first region disposed on the stepped first region of the light-blocking layer and a flat second region disposed on the flat second region of the light-blocking layer.

A pixel is disclosed that includes a light emitting element connected between a first power line and a second power line; a first transistor connected between the first power line and a first electrode of the light emitting element, and having a gate electrode connected to a first node; a second transistor connected between a data line and a second node, and having a gate electrode electrically connected to a first scan line; a third transistor connected between the second node and a third node, having a gate electrode electrically connected to a first light emission control line; and a first capacitor connected between the first node and the third node.

Systems, methods and apparatus are provided for transceiver capacitance reduction. An example apparatus can comprise a first signal driver of a transceiver, a second signal driver of the transceiver, and an input/output (I/O) pad coupled to the first and second signal drivers. The apparatus can further comprise a resistor divider of a plurality of resistor dividers coupled to the first signal driver. The resistor divider, when enabled, can reduce capacitance of the first signal driver and maintain the reduced capacitance while the second signal driver is actively driving a signal.

An electrostatic discharge protection circuit includes: a pulse detection unit, a delay unit, a control unit, and a discharge unit. The pulse detection unit is configured to detect an electrostatic pulse signal; the delay unit is configured to delay or enhance driving capability of the pulse detection signal output by the pulse detection unit; the control unit is configured to generate a control signal based on a first delay signal and a second delay signal output by the delay unit; and the discharge unit is configured to open or close an electrostatic charge discharge passage based on the control signal output by the control unit.

A power metal oxide semiconductor (MOS) transistor die with a temperature sensing function and an integrated circuit are provided. The power MOS transistor die has a control terminal, a phase terminal, a ground terminal and a temperature signal output terminal, and that further includes a power switch part and a temperature sensing part. The power switch part has: a first electrode coupled to the control terminal; a second electrode coupled to the ground terminal; and a third electrode coupled to the phase terminal. The temperature sensing part has: a first electrode; a second electrode coupled to the temperature signal output terminal; and a third electrode coupled to the third electrode of the power switch part. The power switch part and the temperature sensing part are configured as a MOS transistor made by a same manufacturing process, and are capable of sensing temperature precisely.

Provided are a driver circuit which suppresses damage of a semiconductor element due to ESD in a manufacturing process, a method of manufacturing the driver circuit. Further provided are a driver circuit provided with a protection circuit with low leakage current, and a method of manufacturing the driver circuit. By providing a protection circuit in a driver circuit to be electrically connected to a semiconductor element in the driver circuit, and by forming, at the same time, a transistor which serves as the semiconductor element in the driver circuit and a transistor included in the protection circuit in the driver circuit, damage of the semiconductor element due to ESD is suppressed in the process of manufacturing the driver circuit. Further, by using an oxide semiconductor film for the transistor included in the protection circuit in the driver circuit, leakage current in the protection circuit is reduced.

A signal transceiving circuit comprising an IC including a signal transmitting part. The signal transmitting part comprises: a first I/O pad; a second I/O pad; a first output stage circuit, coupled to the first I/O pad; a second output stage circuit, coupled to the second I/O pad; and a first surge protecting device, comprising a first terminal coupled to the first output stage circuit and the first I/O pad, and comprising a second terminal coupled to the second output stage circuit and the second I/O pad.