A thin film transistor can include a substrate, a gate electrode on the substrate, a first electrode located on the substrate and surrounded by the gate electrode, a second electrode located on the first electrode and surrounded by the gate electrode, and a channel layer located between the first electrode and the second electrode. The gate electrode can include a first margin metal layer on the substrate and a second metal layer located on the first margin metal layer. A method for manufacturing the thin film transistor is also provided.

A complementary metal oxide semiconductor (CMOS) device includes a p-channel metal oxide semiconductor (PMOS) transistor unit and an n-channel metal oxide semiconductor (NMOS) transistor unit. A semiconductor layer of the PMOS transistor unit between source and drain electrodes thereof is divided into a first tapered region having an ion concentration of CP/e and a first flat region having an ion concentration of CP/f. A semiconductor layer of the NMOS transistor unit between source and drain electrodes thereof is divided into a second tapered region having an ion concentration of CN/e, a second flat region having an ion concentration of CN/f2 and a third flat region located between the second tapered region and second flat region and having an ion concentration of CN/f1, wherein the ion concentrations have a relationship of CP/e<CP/f<CN/f2<CN/e<CN/f1.

An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

A method of manufacturing a display panel substrate having a semiconductor element includes a film forming step of forming a thin film, a resist film forming step of forming a positive resist film on the thin film, a first exposure step of selectively exposing a resist film via a photomask including a pattern of the semiconductor element, a second exposure step of selectively exposing the resist film by scanning and irradiating the resist film with light along an outline shape of the display panel substrate, a developing step of developing the resist film to remove the resist film exposed in the first and second exposure steps and form a resist pattern on the thin film, an etching step of etching the thin film using the resist pattern as a mask, and forming a thin-film pattern by selectively removing the thin film, and a peeling step of peeling the resist pattern.

Disclosed are an LCD device and a method of manufacturing the same, in which a passivation layer and a pixel electrode are simultaneously formed by a single mask process using a half tone mask, and thus, manufacturing efficiency increases, and a defective contact due to loss of the pixel electrode can be prevented in a pad area. The LCD device includes a pad part including a pad area and a contact area. The LCD device includes a pixel pad formed in the pad area, a pixel bar formed in the contact area, and a bridge layer contacting the pixel pad with the pixel bar. The bridge layer is formed as a single layer or multi layers, and formed of one or more of a transparent conductive material and an opaque conductive material.

A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. A first terminal of the first transistor is connected to a first wiring. A second terminal of the first transistor is connected to a second wiring. A gate and a first terminal of the second transistor are connected to the first wiring. A second terminal of the second transistor is connected to a gate of the first transistor. The first switch is connected between the second wiring and a third wiring. The second switch is connected between the second wiring and the third wiring. The third switch is connected between the gate of the first transistor and the third wiring.

The present disclosure discloses a mask plate, a method of manufacturing a corresponding array substrate, and an array substrate, used in the technical field of liquid crystal displays. The mask plate comprises a non-transparent area and a transparent area. The non-transparent area has an intermediate vertical trunk, an intermediate horizontal trunk, and branches extending from the intermediate vertical trunk and the intermediate horizontal trunk. The intermediate vertical trunk and the intermediate horizontal trunk form certain angles with the branches, respectively. The transparent area has a first transparent portion provided between the branches. The first transparent portion is provided with an optical interference unit, which is used for processing light with a first intensity into light with a second intensity, the first intensity being higher than the second intensity. A second transparent portion is used for directly introducing light with the first intensity to form a contact hole on an array substrate to be formed through the mask plate. The present disclosure further comprises a method of manufacturing an array substrate using the mask plate, and an array substrate thus manufactured. According to the present disclosure, both the aperture ratio of a pixel unit and transmittance of the liquid crystal panel can be improved.

An array substrate for a liquid crystal display device includes a substrate; a semiconductor layer on the substrate; a gate electrode on the semiconductor layer; source and drain electrodes that are on and contact the semiconductor layer; and an oxide layer that corresponds to the semiconductor layer and is on the gate electrode.

A method of manufacturing a low temperature polycrystalline silicon thin film and a thin film transistor, a thin film transistor, a display panel and a display device are provided. The method includes: forming an amorphous silicon thin film (01) on a substrate (1); forming a pattern of a silicon oxide thin film (02) covering the amorphous silicon thin film (01), a thickness of the silicon oxide thin film (02) located at a preset region being larger than that of the silicon oxide thin film (02) located at other regions; and irradiating the silicon oxide thin film (02) by using excimer laser to allow the amorphous silicon thin film (01) forming an initial polycrystalline silicon thin film (04), the initial polycrystalline silicon thin film (04) located at the preset region being a target low temperature polycrystalline silicon thin film (05). The polycrystalline silicon thin film has more uniform crystal size.