A substrate including gate wirings including gate line and a gate electrode disposed on the substrate, a storage line disposed on the same layer as the gate wirings, a gate insulating layer disposed on the gate wirings and the storage line, an oxide semiconductor layer pattern disposed on the gate insulating layer, data wirings including a data line crossing the gate line, a source electrode disposed on one side of the oxide semiconductor layer pattern, and a drain electrode disposed on another side of the oxide semiconductor layer, and an etch stopper including a first etch stopper portion disposed between the storage line and the data line and partially overlapping both the data line and the storage line.

An array substrate, a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof are disclosed. The method for manufacturing the TFT comprises: forming a pattern of an active layer and a gate insulating layer provided with a metal film on a base substrate; patterning the metal film by one patterning process, and forming patterns of a gate electrode, a source electrode, a drain electrode, a gate line and a data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole, a drain contact hole and a bridge structure contact hole; and forming a transparent conductive film on the base substrate, and removing partial transparent conductive film to form a source contact portion, a drain contact portion (214), a pixel electrode and a bridge structure. The manufacturing method can reduce the number of the patterning processes.

A display device according to an embodiment of the present disclosure includes: a substrate; a first conductive layer on the substrate; a first insulating layer on the first conductive layer; an active pattern on the first insulating layer and including a semiconductor material; a second insulating layer on the active pattern; and a second conductive layer on the second insulating layer, wherein the first insulating layer has a first opening exposing the first conductive layer, the second insulating layer has a second opening exposing the first conductive layer, a breadth of the first opening is different than a breadth of the second opening, and a side surface of the first opening and a side surface of the second opening are formed to a top surface of the first conductive layer.

An array substrate includes: a first substrate; a plurality of gate lines and a plurality of data lines; a plurality of thin film transistors; and a plurality of reflective electrodes. The plurality of gate lines and the plurality of data lines define a plurality of sub-pixel regions. A thin film transistor is located in a sub-pixel region. A reflective electrode is located in the sub-pixel region and electrically connected to the thin film transistor in the same sub-pixel region. Each reflective electrode has a border including a plurality of first sub-borders extending in a first direction, a plurality of second sub-borders extending in a second direction, and a plurality of chamfer borders each connecting a first sub-border and a second sub-border that are adjacent; and an intersection of extension lines of the first sub-border and the second sub-border is located outside the border of the reflective electrode.

A preparation method of an oxide thin-film transistor is disclosed, and this method includes: forming a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode; forming of the active layer, the source electrode and the drain electrode includes: sequentially forming an oxide semiconductor thin film and a source-drain electrode metal thin film on a base substrate, an entire surface of the oxide semiconductor thin film being in direct contact with the source-drain electrode metal thin film; and patterning the oxide semiconductor thin film and the source-drain electrode metal thin film with a dual-tone mask so as to form the active layer, the source electrode and the drain electrode by a single patterning process.

A method for manufacturing a dual gate oxide semiconductor TFT substrate utilizes a halftone mask to implement a photo process, which not only accomplishes patterning to an oxide semiconductor layer but also obtains an oxide conductor layer with ion doping. The method implements patterning to a bottom gate isolation layer and a top gate isolation layer at the same time with one photolithographic process. The method implements patterning to second and third metal layers at the same time to obtain a first source, a first drain, a second source, a second drain, a first top gate and a second top gate with one photolithographic process. The method implements patterning to a second flat layer, a passivation layer and a top gate isolation layer at the same time with one photolithographic process. The number of photolithographic processes involved is reduced to nine so as to simplify the manufacturing process.

A variable capacitor is formed from a pair of electrodes and a dielectric interposed between the electrodes over a substrate, and an external input is detected by changing capacitance of the variable capacitor by a physical or electrical force. Specifically, a variable capacitor and a sense amplifier are provided over the same substrate, and the sense amplifier reads the change of capacitance of the variable capacitor and transmits a signal in accordance with the input to a control circuit.

A dual gate oxide semiconductor thin-film transistor (TFT) substrate includes a substrate; a bottom gate positioned on the substrate; a bottom gate isolation layer positioned on the substrate and the bottom gate; a first oxide semiconductor layer positioned on the bottom gate isolation layer above the bottom gate; an oxide conductor layer positioned on the bottom gate isolation layer at one side of the first oxide semiconductor layer; a top gate isolation layer positioned on the first oxide semiconductor layer, the oxide conductor layer, and the bottom gate isolation layer; a top gate positioned on the top gate isolation layer above a middle part of the first oxide semiconductor layer; a source and a drain positioned on the top gate isolation layer at two sides of the top gate; and a passivation layer positioned on the top gate isolation layer, the source, the drain, and the top gate.

The present disclosure discloses a panel structure of flat displays and the manufacturing method thereof. The panel structure includes a first signal line, a second signal line, a transparent conductive film, and a scanning line. The transparent conductive film includes a first branch, a second branch, and a third branch. A first end of the first branch and a first end of the second branch are connected by a predetermined first angle, and a second end of the second branch and a first end of the third branch are connected by a predetermined second angle. The first branch, the second branch, and the third branch form the arch-shaped frame. The first signal line connects to the second end of the first branch, and the second signal line connects to the second end of the third branch. The scanning line passes through the arch-shaped frame along a first direction.

A TFT substrate, a TFT switch and a manufacturing method for the same are disclosed. The method includes steps of disposing a gate electrode layer on a substrate, thinning at least a portion of each side region along a thickness direction of the gate electrode layer in order to form two thin regions, disposing a semiconductor layer above the gate electrode layer, and disposing a source electrode layer and a drain electrode layer on the semiconductor layer, wherein, a contact region between the source electrode layer and the semiconductor layer, and a contact region between the drain electrode layer and the semiconductor layer are respectively corresponding to the two thin regions. The present invention can omit a doping process in order to achieve a good ohmic contact so as to solve a schottky contact problem.