A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a gate layer on the substrate; forming a first gate dielectric layer on the gate layer; forming a first channel layer on the first region and a second channel layer on the second region; and forming a first source/drain on the first channel layer and a second source/drain on the second channel layer.

A thin film transistor (TFT) located on a thin film transistor substrate includes a first insulating film formed so as to cover a gate electrode, a channel layer that is formed at a position on the first insulating film overlapping the gate electrode and formed of an oxide semiconductor, a second insulating film formed on the channel layer, and a third insulating film formed so as to cover the second insulating film. A source electrode and a drain electrode are formed on the third insulating film. Each of the source electrode and the drain electrode is connected to the channel layer through the corresponding one of contact holes penetrating the second insulating film and the third insulating film.

The invention relates to the field of display technologies, and discloses a method for producing a via, a method for producing an array substrate, an array substrate and a display device to prevent a chamfer from being formed in producing the via, to promote the product quality and improve the display effect of the display device. The method for producing a via comprises: employing a first etching process to partially etch a top film layer in an area that needs to form a via above an electrode, wherein the vertical etching amount achieved by employing the first etching process is less than the thickness of the top film layer; and employing a second etching process for which the vertical etching rate is larger than the lateral etching rate to etch the remaining part in the area that needs to form a via, until the electrode is exposed.

A memory device includes a plurality of memory cells. A first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. A first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. The first read source is coupled to the first write source. A first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor.

According to an embodiment of the disclosure, a display device may include an active layer, a gate electrode disposed on the active layer, a first insulating layer disposed on the gate electrode, entirely covering the gate electrode, and including a flat surface, and a second insulating layer disposed on the first insulating layer and including a flat surface, and the first insulating layer and the second insulating layer may include inorganic materials different from each other.

A touch panel includes: a substrate; a first metallic layer for forming a gate of a thin-film transistor (TFT); a gate insulating layer; a second metallic layer for forming a data line, a source and a drain of the TFT; an isolation layer penetrated by a first hole; a third metallic layer for forming a driving line for transmitting a driving signal and a common voltage; a passivation layer, layered with and deposited on the isolation layer, penetrated by the first hole and a second hole, and the second hole aiming at the data line; a pixel electrode, connected to the source or the drain through the first hole; a driving electrode, connected to the driving line through the second hole; and a sensing electrode, for transmitting a sensing signal and the common voltage. The driving electrode and the sensing electrode are used as common electrode layers.

A display panel includes first and second test lines connected to the each of data lines, extending in the second direction, and arranged in the first direction, a first test pad electrically connected to the first test line, the first test pad and the first test line being formed from a same layer, and a second test pad electrically connected to the second test line through a contact hole formed through a first insulation layer and disposed adjacent to the first test pad in the second direction.

An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.

The present invention provides an array substrate and a manufacturing method thereof. Etching stop patterns or auxiliary conductive patterns of a patterned auxiliary conductive layer are disposed corresponding to heavily doped regions of a patterned semiconductor layer, and source/drain electrodes may be electrically connected to the heavily doped regions via the etching stop patterns or the auxiliary conductive patterns. The production yield and the uniformity of electrical properties may be enhanced accordingly.

A semiconductor device that can retain data for a long time is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor contains an oxide semiconductor in a channel formation region. The second transistor includes a first gate and a second gate. A gate of the first transistor is connected to a first electrode of the first transistor. The first electrode of the first transistor is connected to the second gate. A negative potential is applied to a second electrode of the first transistor. The first electrode and the second electrode of the first transistor include a first end portion and a second end portion, respectively. The first end portion and the second end portion face each other. The first end portion includes a first arc and the second end portion includes a second arc when seen from the top. The radius of curvature of the second arc is larger than that of the first arc.