NON-VOLATILE MEMORY WITH DUAL GATED CONTROL

Abstract

A memory device includes a plurality of memory cells. A first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. A first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. The first read source is coupled to the first write source. A first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor.

Claims

1. A memory device, comprising: a first transistor comprising a gate, a source, and a drain; a second transistor comprising a gate, a source, a drain, and a body region separating the source of the second transistor from the drain of the second transistor, wherein the source of the second transistor is coupled to the source of the first transistor; and a capacitor having a first capacitor plate and a second capacitor plate, the first capacitor plate coupled to the drain of the first transistor and the second capacitor plate coupled to the body region of the second transistor, and wherein the capacitor is configured to selectively store at least two different levels of body bias charge, respectively, that change a voltage threshold of the second transistor between at least two different voltage threshold levels, respectively, whereby the at least two different voltage threshold levels, respectively, correspond to at least two predetermined data states, respectively, of the memory device.

2. The memory device of claim 1, further comprising: a write wordline coupled to the gate of the first transistor; a write bitline coupled to the source of the first transistor and the source of the second transistor; and write bias circuitry coupled to the write wordline and the write bitline, the write bias circuitry configured to selectively store the at least two different levels of body bias charge on the capacitor to thereby write the at least two predetermined data states to the memory device.

3. The memory device of claim 2, further comprising: a read wordline coupled to the gate of the first transistor; a read bitline coupled to the drain of the second transistor; and read bias circuitry coupled to the drain of the second transistor, the read bias circuitry configured to determine a data state stored in the memory device by determining whether the voltage threshold set by the body bias charge stored on the capacitor is greater than or less than a predetermined voltage threshold.

4. The memory device of claim 3, wherein the write wordline and the read bitline extend in parallel with one another upward from an upper surface of a semiconductor substrate.

5. The memory device of claim 1, wherein the first capacitor plate is in direct electrical connection with only the drain of the first transistor and the second capacitor plate is in direct electrical connection with only the body region of the second transistor.

6. The memory device of claim 1, further comprising: a third transistor comprising a gate, a source, and a drain; a fourth transistor comprising a gate, a source, a drain, and a body region separating the source of the fourth transistor from the drain of the fourth transistor, wherein the source of the fourth transistor is coupled to the source of the third transistor; a second capacitor having a first capacitor plate and a second capacitor plate, the first capacitor plate of the second capacitor coupled to the drain of the third transistor and the second capacitor plate of the second capacitor coupled to the body region of the fourth transistor; and a wordline coupled to the gate of the first transistor and the gate of the third transistor.

7. A semiconductor memory structure, comprising: a semiconductor substrate; a first conductive line extending upwardly over an upper surface of the semiconductor substrate; a first gate dielectric disposed along a first side of the first conductive line; a second conductive line extending upwardly from an upper surface of the semiconductor substrate and laterally spaced apart from the first conductive line; a second gate dielectric disposed over an upper surface of the second conductive line; a semiconductor region disposed over the second gate dielectric and to a side of the first gate dielectric furthest from the first conductive line; a conductive feature disposed over the semiconductor region; a capacitor dielectric disposed over the semiconductor region and disposed to a side of the conductive feature; and a first capacitor plate disposed over the conductive feature and over the capacitor dielectric.

8. The semiconductor memory structure of claim 7, wherein the semiconductor region comprises: a first body region proximate to the side of the first gate dielectric, a second body region over the second gate dielectric and over the upper surface of the second conductive line, and a second capacitor plate region along an upper surface of the semiconductor region and spaced apart from the first gate dielectric by the first body region.

9. The semiconductor memory structure of claim 7, further comprising: a third conductive line extending along a second side of the semiconductor region opposite the first gate dielectric.

10. The semiconductor memory structure of claim 9, wherein the third conductive line directly contacts the second side of the semiconductor region.

11. The semiconductor memory structure of claim 7, further comprising: a first write bitline disposed between the upper surface of the semiconductor substrate and a lower surface of the semiconductor region, and disposed laterally between the first conductive line and the second conductive line.

12. The semiconductor memory structure of claim 7, wherein the semiconductor region is a four-sided polygon as viewed in cross-section.

13. The semiconductor memory structure of claim 7, further comprising: a second semiconductor region disposed over an upper surface of the first capacitor plate; and wherein the first conductive line extends along a first side of the second semiconductor region, the first conductive line being separated from the first side of the second semiconductor region by the first gate dielectric.

14. The semiconductor memory structure of claim 9, further comprising: a second semiconductor region disposed over an upper surface of the first capacitor plate; wherein the first conductive line extends along a first side of the second semiconductor region, the first conductive line being separated from the first side of the second semiconductor region by the first gate dielectric; and wherein the third conductive line extends along a second side of the second semiconductor region opposite the first side of the second semiconductor region and is coupled to the second semiconductor region.

15. The semiconductor memory structure of claim 9, wherein the first conductive line, the first gate dielectric, the second conductive line, the second gate dielectric, the semiconductor region, the conductive feature, the capacitor dielectric, and the first capacitor plate correspond to a first memory cell, and further comprising: a second memory cell that is disposed to a side of the third conductive line opposite the first memory cell, wherein the second memory cell is a mirror image of the first memory cell about the third conductive line.

16. A memory device, comprising: a first transistor comprising a gate, a source, a body, and a drain, wherein the body of the first transistor is disposed in a region of semiconductor material over a semiconductor substrate; a first conductive line coupled to the gate of the first transistor, the first conductive line extending upwards over an upper surface of the semiconductor substrate and past a sidewall of the region of semiconductor material; a second transistor comprising a gate, a source, a body, and a drain, wherein the body of the second transistor is disposed in the region of semiconductor material; and a capacitor having a first capacitor plate and a second capacitor plate, the first capacitor plate coupled to the drain of the first transistor and the second capacitor plate disposed in the region of semiconductor material.

17. The memory device of claim 16, wherein the capacitor is configured to selectively store at least two different levels of body bias charge, respectively, that change a voltage threshold of the second transistor between at least two different voltage threshold levels, respectively, whereby the at least two different voltage threshold levels, respectively, correspond to at least two predetermined data states, respectively, of the memory device.

18. The memory device of claim 17, wherein the first conductive line is coupled to the gate of the first transistor, and further comprising: a second conductive line coupled to the source of the first transistor and the source of the second transistor; and write bias circuitry coupled to the first conductive line and the second conductive line, the write bias circuitry configured to selectively store the at least two different levels of body bias charge on the capacitor to thereby write the at least two predetermined data states to the memory device.

19. The memory device of claim 18, further comprising: a third conductive line coupled to the gate of the second transistor; a fourth conductive line coupled to the drain of the second transistor; and read bias circuitry coupled to the drain of the second transistor, the read bias circuitry configured to determine a data state stored in the memory device by determining whether the voltage threshold set by the body bias charge stored on the capacitor is greater than or less than a predetermined voltage threshold.

20. The memory device of claim 19, wherein the first conductive line and the fourth conductive line extend in parallel with one another upwardly from an upper surface of the semiconductor substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0004] FIG. 1 depicts a schematic representation of some embodiments of a two-transistor memory cell.

[0005] FIG. 2 depicts a cross-sectional view of some embodiments of a memory cell that is disposed over a semiconductor substrate and is consistent with FIG. 1's schematic representation.

[0006] FIG. 3 depicts a schematic representation of some embodiments of an array including eight two-transistor memory cells.

[0007] FIG. 4 depicts a cross-sectional view of some embodiments of eight two-transistor memory cells disposed over a semiconductor substrate consistent with FIG. 3's schematic representation.

[0008] FIG. 5 depicts a schematic representation of some embodiments of an array including sixteen two-transistor memory cells.

[0009] FIGS. 6-8 depict a cross-sectional view and various perspective cut-away views of some embodiments of an array of two-transistor memory cells consistent with FIG. 5s schematic representation.

[0010] FIGS. 9-29 depict a series of cross-sectional and perspective views that collectively depict a manufacturing flow for making a memory device.

[0011] FIG. 30 depicts a flow chart that depicts a manufacturing flow in accordance with some embodiments.

DETAILED DESCRIPTION

[0012] The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

[0013] Further, spatially relative terms, such as beneath, below, lower, above, upper and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0014] FIG. 1 illustrates an example schematic of a memory cell 100 in accordance with some embodiments. The memory cell 100 includes two transistorsnamely a write transistor 102 and a read transistor 104and a capacitor 106, which are operably coupled as shown. More particularly, the write transistor 102 includes a write gate (G1), a write source (S1), a write drain (D1), and a write body region (B1) that separates the write source (S1) from the write drain (DI). The read transistor 104 includes a read gate (G2), a read source (S2), a read drain (D2), and a read body region (B2) that separates the read source (S2) from the read drain (D2). The read source (S2) is coupled to the write source (S1), both of which are coupled to a write bitline (WBL) 108. The capacitor 106 has an upper capacitor plate (C1) coupled to the write drain (D1) and a lower capacitor plate (C2) coupled to the body region (B2) of the read transistor 104. A capacitor dielectric (Cox) separates the upper capacitor plate (C1) from the lower capacitor plate (C2). It will be appreciated that the naming convention of source and drain as used herein is somewhat arbitrary, and these terms can be interchanged in other embodiments and/or can be alternatively referred to as source/drain regions.

[0015] A write wordline (WWL) 110 is coupled to the write gate (G1). Write bias circuitry 112 is coupled to the write bitline WBL 108 and write wordline WWL 110. The write bias circuitry 112 is configured to write/store various predetermined amounts of charge on the capacitor 106, wherein the predetermined amounts of stored charge set a voltage threshold of the read transistor 104 to correspond to one of at least two predetermined data states. A read wordline (RWL) 114 is coupled to the read gate (G2), and a read bitline (RBL) 116 is coupled to the read drain (D2). Read circuitry 118 is coupled to the RWL 114 and RBL 116. The read circuitry 118 is configured to determine a data state stored in the memory cell 100 by determining whether the voltage threshold set by the amount of charge stored on the capacitor 106 is greater than or less than a predetermined voltage threshold.

[0016] In some embodiments (see Table 1 below), the memory cell 100, write bias circuitry 112, and read circuitry 118 can be configured such that a single bit of data that is either in a 0 data state or a 1 data state is stored in the memory cell 100. In other embodiments (see Table 2 below), the memory cell 100, write bias circuitry 112, and read circuitry 118 can be configured such that multiple bits of data (e.g., two bits or more of data) is stored in the memory cell 100.

[0017] Table 1 illustrates some embodiments of how the write bias circuit 112 and read circuit 118 can bias the WBL 108, WWL 110, RWL 114, and RBL 116 to write a single bit (e.g., either a 0 state or a 1 state) to the memory cell 100 and to read the various data states from the memory cell 100.

TABLE-US-00001 TABLE 1 example bias conditions for single-bit reads/writes WWL WBL RWL RBL single bit 0 Vdd Gnd Gnd Gnd/Float single bit 1 Vdd Vwrite Gnd Gnd/Float Read Gnd Gnd Vread Vdd

[0018] As noted above, generally the amount of charge stored on the capacitor 106 can be set to one of various predetermined charge levels that set the threshold voltage of the read transistor 104 to one of various predetermined threshold voltages, whereby the various predetermined threshold voltages correspond to different data states. For example, in some embodiments, the memory cell 100 can store a single bit that is either a 0 or a 1. Thus, in Table 1, to write a single-bit 0, the WWL 110 is driven to Vdd to enable the write transistor 102, and while the WWL 110 is held at Vdd, the WBL 108 is taken to Ground, which strips charge off the capacitor 106 and correspondingly decreases the body bias applied to the body (B2) of the read transistor 104. The WWL 110 is then de-asserted (e.g., taken to ground), such that the low-charge condition remains on the capacitor 106 in a non-volatile fashion. In contrast, to write a single-bit 1 to the memory cell 100, the WWL 110 is driven to Vdd to enable the write transistor 102, and the WBL 108 is concurrently held at Vwrite (e.g., Vdd or other appropriate voltage) which adds charge onto the capacitor 106 and correspondingly increases the body bias applied to the body (B2) of the read transistor 104. The WWL 110 is then de-asserted (e.g., taken to ground), such that this high-charge condition remains on the capacitor 106 in a non-volatile fashion. Because the voltage threshold of the read transistor 104 changes based on its body bias (and hence, charge stored on the capacitor 106), the read transistor 104 exhibits different threshold voltages for the 0 data state and the 1 data state. Thus, for a read operation, the WWL 110 and WBL 108 are grounded, the RWL 114 is driven to a Vread voltage (e.g., a high voltage) to selectively enable the read transistor 104, and the RBL 116 is driven to VDD. Under this bias condition, the source/drain voltage over the read transistor 104 (and/or amount of current flowing through the read transistor 104) is based on how the Vread voltage relates to the voltage threshold of the read transistor (and hence also relates to the body bias applied to the read transistor 104 and the amount of charge stored in the capacitor 106). Thus, if a small amount of charge is stored in the capacitor 106 (e.g., logical 0 and small body bias), the voltage threshold of the read transistor 104 is greater than Vread, and little or no current will flow over the read transistor 104 during the read operation. In contrast, if a large amount of charge is stored on the capacitor 106 (e.g., logical 1 and large body bias), the voltage threshold of the read transistor 104 is less than Vread, and more current will flow over the read transistor 104 during the read operation. The read circuitry 118 can measure the voltage bias between the read source S2 and read drain D2 (and/or can measure the current between the read source S2 and read drain D2) to determine whether a 0 data state or a 1 data state was stored in the memory cell 100.

[0019] Table 1 illustrates an example of how the write bias circuit 112 and read circuitry 118 in other embodiments can bias the WBL 108, WWL 110, RWL 114, and RBL 116 to write a multi-bit state to the memory cell 100 and to read the various data states from the memory cell 100.

TABLE-US-00002 TABLE 2 example bias conditions for multi-bit reads/writes WWL WBL RWL RBL Write dual bit 00 Vdd Gnd Gnd Gnd/Float Write dual bit 11 Vdd Vwrite Gnd Gnd/Float Write dual bit 01 Vdd Vwrite k1 Gnd Gnd/Float Write dual bit 10 Vdd Vwrite k2 Gnd Gnd/Float Read Gnd Gnd Vread Vdd

[0020] Table 2 shows another example of bias conditions that can be applied to store multiple bits in the memory cell at a given time. In this example, the memory cell stores two bits at a given time that represent four data states, but it will is appreciated in general any number of bits can be stored. In this example, k1 can be for example and k2 can be for example, but other values are also possible to provide adequate spacing between the various write data states.

[0021] Turning now to FIG. 2, one can see a cross-sectional view of a memory cell 200 that is disposed over a semiconductor substrate 202. The memory cell 200 of FIG. 2 is consistent with FIG. 1's schematic, and thus includes a write transistor 102, read transistor 104, and capacitor 106 that are operably coupled as described in FIG. 1. It will be appreciated that the schematic of FIG. 1 may manifest in various forms, and the implementation of FIG. 2 offers various advantages from performance and manufacturing perspectives but is a non-limiting example of how FIG. 1's schematic can be implemented.

[0022] As shown in FIG. 2, these components of the memory cell 200 are disposed on a semiconductor substrate 202. The semiconductor substrate 202 can manifest as a monocrystalline silicon substrate, a semiconductor on insulator (SOI) substrate, or another substrate; and can include multiple substrates and/or interconnect structures stacked over one another.

[0023] As shown, the memory cell 200 includes a body region 204, which comprises a semiconductor material such as Indium gallium zinc oxide (IGZO), Indium tin oxide (ITO), Indium tungsten zinc oxide (IWZO), and/or channel materials with low off-current across temperature disposed over an upper surface of the semiconductor substrate 202. The body region 204 can correspond to the body (B1) of the write transistor 102, the body (B2) of the read transistor 104, and the lower capacitor plate (C2) of the capacitor 106.

[0024] A write wordline WWL 110 extends along a first side of the body region 204, though WWL 110 is separated from the first side of the body region 204 by a write wordline gate dielectric 206. A read bitline (RBL) 116 extends along a second side of the body region 204 opposite the first side and is coupled to the body region 204. A write bitline (WBL) 108 is disposed between the upper surface of the semiconductor substrate 202 and a lower surface of the body region 204, and is disposed between the WWL 110 and the RBL 116. A read wordline (RWL) 114 is also disposed between the upper surface of the semiconductor substrate 202 and the lower surface of the body region 204, and is disposed between the WBL 108 and the RBL 116. The RWL 114 is separated from the lower surface of the body region 204 by a read wordline gate dielectric 208.

[0025] In some embodiments, the write wordline gate dielectric 206 and the read wordline gate dielectric 208 may comprise a dielectric material, such as silicon dioxide or a high-k dielectric, such as hafnium oxide (HfO2). In some embodiments, the WWL 110, RBL 116, WBL 108, and RWL 114 comprise a metal, such as tungsten (W), copper (Cu), aluminum (Al), Titanium nitride (TiN), or tantalum nitride (TaN), or a CMOS contact metal, among others; doped polysilicon; or another conductive material.

[0026] The capacitor 106 is disposed over an upper surface of the body region 204 and is disposed between the WWL 110 and the RBL 116. The capacitor 106 is configured to selectively store varying levels of charge corresponding to varying data states on the body region 204. In particular, the capacitor 106 can include an upper capacitor plate (C1) 210 which is coupled to the drain (D1) 230 of the write transistor 102, a lower capacitor plate (C2) corresponding to the body region 204, and a capacitor dielectric 212 disposed between the upper capacitor plate (C1) and lower capacitor plate (C2). The upper capacitor plate 210 and the drain (D1) 230 of the write transistor 102 can comprise doped semiconductor material (e.g., p-doped or n-doped silicon), or a metal, such as tungsten (W), copper (Cu), aluminum (Al), Titanium nitride (TiN), tantalum nitride (TaN), or a CMOS contact metal, among others. The capacitor dielectric 212 can comprise silicon dioxide or a high-k dielectric, and in some embodiments can comprise aluminum oxide (Al2O3), Hafnium oxide (HfO2), tantalum oxide (Ta2O5), Zirconium oxide (ZrO2), Titanium oxide (TiO2), strontium titanium oxide (SrTiO3), or another high-k dielectric material, among others.

[0027] Dielectric regions (214, 216, 218, 220, and 222), such as silicon dioxide or a low-k dielectric, can provide electrical isolation between the conductive features within the memory cell 200. Further dielectric regions 224 and 226 can provide electrical isolation between the memory cell 200 and the substrate 202, and/or between the memory cell 200 and additional memory cells stacked above or below the memory cell 200. In some embodiments, the further dielectric regions 224 and 226 can be a nitride, such as silicon nitride or silicon oxynitride, but in other embodiments can be another dielectric material such as silicon dioxide, silicon carbide oxide, or others.

[0028] In some embodiments, the write wordline WWL 110 extends vertically and continuously from an upper surface of the capacitor (e.g., top surface of 210) to a bottom surface of the write bitline WBL 108 or to a bottom surface of the read wordline RWL 114. In some embodiments, the read bitline RBL 116 also extends vertically and continuously from an upper surface of the first capacitive element (e.g., top of 210) to a bottom surface of the write bitline WBL 108 or to a bottom surface of the read wordline RWL 114.

[0029] Although FIG. 2 illustrates only a single memory cell 200, it will be appreciated that any number of such memory cells can be stacked over the illustrated memory cell, to the left or the right of the illustrated memory cell, or even between the illustrated memory cell and the substrate 202. Some non-limiting examples of how such memory cells can be arranged are now illustrated and described in FIGS. 3-8.

[0030] FIG. 3 depicts a schematic drawing including eight memory cells that are included in a portion of a memory array, and FIG. 4 depicts a cross-sectional view of eight memory cells consistent with FIG. 3's schematic. FIG. 3-4 are now described concurrently in the context of a first memory cell (e.g., 200-1-1), second memory cell (e.g., 200-1-2), third memory cell (e.g., 200-0-1), and fourth memory cell (e.g., 200-2-1); but it will be appreciated that in general first, second, third, fourth and the like are merely generic identifiers and these identifiers can in general be used to describe any of memory cells of FIG. 3 and/or the various identifiers can be transposed or interchanged in other embodiments. Each of the memory cells in FIG. 3 can correspond to the schematic and functionality described with regards to FIG. 1, and can correspond to the cross-section described with regards to FIG. 2.

[0031] In FIGS. 3-4, a first memory cell 200-1-1 comprises a first write transistor 102-1-1 comprising a first write gate WWL1 110-1, a first write source WBL1A-1, and a first write drain 230-1-1; and a first read transistor 104-1-1 comprising a first read gate RWL1-1, a first read source WBLIA-1, a first read drain RBL1 (116-1), and a first body region 204-1-1 separating the first read source from the first read drain. The first read source WBL1A-1 is the same node as the first write source WBL1A-1. A first capacitor 106-1-1 has a first upper capacitor plate 210-1-1 coupled to the first write drain 230-1-1 and a first lower capacitor plate 204-1-1 corresponding to the first body of the first read transistor 104-1-1.

[0032] A second memory cell 200-1-2 is disposed over the first memory cell 200-1-1. The first write wordline WWL1 extends alongside the first memory cell 200-1-1 and the second memory cell 200-1-2. The second memory cell 200-1-2 comprises: a second write transistor 102-1-2 comprising a second write gate corresponding to WWL1 110-1, a second write source WBL1A-2, and a second write drain 230-1-2; and a second read transistor 104-1-2 comprising a second read gate RWL1-2, a second read source WBL1A-2, a second read drain RBL1, and a second body region 204-1-2 separating the second read source from the second read drain. The second read source WBL1A-2 is the same node as the second write source WBL1A-2. A second capacitor 106-1-2 has a second upper capacitor plate 210-1-2 coupled to the second write drain 230-1-2 and a second lower capacitor plate corresponding to the second body 204-1-2 of the second read transistor. A second write bitline WBL1A-2 is disposed between the upper surface of the first capacitive element and a lower surface of the second body region 204-1-2, and is disposed between the first write wordline WWL1 and the first read bitline RBL1. A second read wordline RWL1-2 is disposed between the upper surface of the first capacitive element and the lower surface of the second body region 204-1-2, and is disposed between the first write wordline WWL1 and the first read bitline RBL1. The second read wordline RWL1-2 is separated from the lower surface of the second body region 204-1-2 by a second read wordline gate dielectric 208. A second capacitor 106-1-2 is disposed over an upper surface of the second body region 204-1-2 and is disposed between the first write wordline WWL1 and the first read bitline RBL1. The second capacitor is configured to selectively store varying levels of charge corresponding to varying data states on the second body region 204-1-2.

[0033] A third memory cell 200-0-1 is disposed alongside the first memory cell 200-1-1 (e.g., to the right of the first memory cell 200-1-1 in FIGS. 3-4). The third memory cell 200-0-1 includes a third write transistor 102-0-1 comprising a third write gate WWL0, a third write source 230-0-1, and a third write drain WBL0B-1; and a third read transistor 104-0-1 comprising third read gate RWL0-1, a third read source WBL0B-1, a third read drain RBL1, and a third body region 204-0-1 separating the third read source WBL1A-1 from the third read drain RBL1. The third read source WBL0B-1 is the same node as the third write source. A third capacitor 106-0-1 has a third upper capacitor plate 210-0-1 coupled to the third write drain 230-0-1 and a third lower capacitor plate corresponds to the third body 204-0-1 of the third read transistor. The first read bitline RBL1 extends between the first memory cell 200-1-1 and the third memory cell 200-0-1. The first read bitline RBL1 is coupled to the first body region 204-1-1 and the third body region 204-0-1. The first memory cell 200-1-1 and third memory cell 200-0-1 are mirror images of one another about the first read bitline RBL1.

[0034] A fourth memory cell 200-2-1 is disposed alongside the first memory cell 200-1-1 (e.g., to the left of the first memory cell 200-1-1 in FIGS. 3-4). The fourth memory cell 200-2-1 comprises a fourth body region 204-2-1 disposed over the upper surface of the semiconductor substrate 202 and to a side of the first write wordline WWL1 opposite the first body region 204-1-1; a second read bitline RBL2 extending along a side of the fourth body region 204-2-1 furthest from the first body region 204-1-1 and coupled to the fourth body region 204-2-1. A fourth write bitline WBL1B-1 is disposed between the upper surface of the semiconductor substrate 202 and a lower surface of the fourth body region 204-2-1, and is disposed between the first write wordline WWL1 and the second read bitline RBL2. A fourth read wordline RWL2-1 is disposed between the upper surface of the semiconductor substrate 202 and the lower surface of the fourth body region 204-2-1, and is disposed between the first write wordine WWL1 and the second read bitline RBL2. The fourth read wordline RWL2-1 is separated from the lower surface of the fourth body region 204-2-1 by a fourth read wordline gate dielectric 208. A fourth capacitor 106-2-1 is disposed over an upper surface of the fourth body region and is disposed between the first write wordline WWL1 and the second read bitline RBL2. The fourth capacitor 106-2-1 is configured to selectively store varying levels of charge corresponding to varying data states on the fourth body region 204-2-1, and includes a fourth upper capacitor electrode 210-2-1 and a fourth lower capacitor electrode corresponding to the fourth body region 204-2-1.

[0035] FIG. 5 shows a schematic view of a three-dimensional array including sixteen memory cells organized in two aisles of eight memory cells, with each aisle containing eight memory cells arranged in two rows and four columns. FIG. 6 depicts a cross-sectional view of an aisle of eight memory cells consistent with FIG. 5's schematic, and FIGS. 7-8 depict various perspective cutaway views of the three-dimensional array of FIG. 5 (along with additional memory cells in additional aisles) with cutaways as indicated in FIG. 6. As shown in FIGS. 5-8, in these embodiments write word lines (WWL) and read bitline (RBL) extend vertically and alternatingly between stacks of memory cells. The WWLs are coupled to gates of the neighboring write transistors, and the RBLs are coupled to drains of the neighboring read transistors. Read Wordlines (RWL) and Write Bitlines (WBL) extend continuously into the page between neighboring aisles of memory cells, and are operably coupled as shown.

[0036] Turning now to FIGS. 9-29, one can see a series of cross-sectional views and corresponding perspective views that illustrate a method of manufacturing a memory device in accordance with some embodiments.

[0037] In FIG. 9, a number of layers are deposited over a semiconductor substrate 202. The layers may include multiple memory stacks (e.g., first memory stack 902a, second memory stack 902b, . . . ) that are stacked over one another, wherein each memory stack includes a lower dielectric isolation layer 226, an oxide layer 222, a gate dielectric layer 208, a body layer 204, a capacitor dielectric layer 212, an upper capacitor metal layer 210, and an upper dielectric isolation layer 226 (which may be merged with or one in the same as the lower dielectric isolation layer 224 for higher memory stacks). In some embodiments, the bottom-most memory stack (e.g., 902a) is optionally separated from the semiconductor substrate 202 by the dielectric isolation region 226, which may be a standalone layer or may include in a back-end-of-line (BEOL) interconnect structure that includes multiple dielectric layers and horizontal wiring layers and vertical vias that are coupled to semiconductor devices (e.g., transistors) in the semiconductor substrate 202. Dielectric walls 904 are also disposed in the structure to provide isolation between neighboring regions of the memory stacks in the y-direction).

[0038] In FIG. 10, a first mask (not shown), such as a photomask is patterned over the uppermost memory stack (e.g., 902b), and a first vertical etch is carried out with the first mask in place. Thus, the first vertical etch can be a wet etch or dry etch can proceed down to the substrate 202. As such, in FIG. 10, six aisles of patterned memory stack structures are formed and are separated from one another by RBL trenches 1002 and WWL trenches 1004, though it will be appreciated that in general any number of memory stack structures can be formed. Each patterned memory stack structure can include a lower dielectric isolation layer 226, an oxide layer 222, a gate dielectric layer 208, a body layer 204, a capacitor dielectric layer 212, an upper capacitor metal layer 210, and an upper dielectric isolation layer 226 (which may be merged with or one in the same as the lower dielectric isolation layer 224 for higher memory stacks). Whereas the structure in FIG. 10 illustrates vertical sidewalls, the first vertical etch can also have a slight lateral component resulting in sidewalls that are slanted such that structures nearer the substrate 202 are wider, and structures further from the substrate 202 are narrower (see lines 1006). The same is true of other etches presented herein.

[0039] In FIG. 11, with the first mask still in place, a first lateral etch, such as a wet etch for example, is carried out to remove outermost portions of the upper capacitor metal region in each memory stack structure, and forming first recesses 1102. In some embodiments, the first lateral etch can comprise SC1 (a mixture of NH.sub.4OH and H.sub.2O.sub.2), SC2 (a mixture of HCl and H.sub.2O.sub.2) and/or SPM (a mixture of H.sub.2SO.sub.4 and H.sub.2O.sub.2) in the case for TiN. Thus, the first lateral etch can be selective to remove the outermost portions of the upper capacitor metal regions while leaving the other layers of the stack substantially in place.

[0040] In FIG. 12, a dielectric 1200 is formed over an upper surface of the memory stack regions, along sidewalls of the memory stack regions, and over an exposed upper surface of the semiconductor substrate between the memory stack regions. In some embodiments, the dielectric 1200 entirely fills the RBL trenches 1002 and WWL trenches 1004. The dielectric 1200 can comprise silicon dioxide in some embodiments, but can also be a low-k dielectric in other embodiments. A CMP may be performed after dielectric 1200 is formed so upper surface of dielectric 1200 is planarized with the upper surface of isolation layer 224/226.

[0041] In FIG. 13, a second mask (not shown), such as a photomask is patterned over the uppermost memory stack, and a wet or dry etch is carried out with the second mask in place to re-open the RBL trenches 1002 by removing the dielectric 1200 from those trenches, while leaving the WWL trenches filled with dielectric 1200. The wet etch or dry etch can proceed down to the substrate 202.

[0042] In FIG. 14, a second lateral etch is carried out to remove an outermost portion of the dielectric 1200 from the re-opened RBL trenches, thereby forming recesses 1402 in outer edges of the re-opened RBL trenches. In some embodiments, this second lateral etch is a wet etch or a dry etch and comprises a halogen, such as fluorine.

[0043] In FIG. 15, a conductive material 1500 is deposited to fill in the re-opened RBL trenches and to fill in the corresponding recesses. In some embodiments, the conductive material 1500 is formed by a physical deposition process, such as sputtering, electroplating, atomic layer deposition, or physical vapor deposition. In some embodiments, the conductive material 1500 is a metal, and can comprise ruthenium, or tungsten because of tungsten's good fill properties and affinity for filling small gaps without forming voids. Further in FIG. 15, after the conductive material has been formed to fill the re-opened RBL trenches and corresponding recesses, a vertical metal etch is performed to re-open the RBL trenches while leaving the conductive material 1500 in the recesses, as shown in FIG. 15.

[0044] In FIG. 16, a third lateral etch is carried out to remove an outermost portion of the conductive material 1500 from the recesses, thereby forming shallow recesses 1602 in outer edges of the RBL trenches 1002. In some embodiments, this third lateral etch is a wet etch or a dry etch and comprises fluorine.

[0045] In FIG. 17, a dielectric is formed to entirely or partially fill the re-opened RBL trenches 1002 and the shallow recesses 1602 of FIG. 16. The dielectric can comprise silicon dioxide in some embodiments, but can also be a low-k dielectric in other embodiments. After the dielectric is formed to fill the re-opened RBL trenches and the shallow recesses, a vertical etch is performed to re-open the RBL trenches 1002 and the WWL trenches 1004, while leaving dielectric material 1700 in the shallow recesses (1602 of FIG. 17), and leaving dielectric material 1200 along other sidewalls of the memory stacks. In some embodiments dielectric material 1700 and dielectric material 1200 may be the same composition as one another, but in other embodiments may have different composition from one another.

[0046] In FIG. 18, a conductive material 1800 is deposited to fill in the re-opened RBL trenches 1002 and the re-opened WWL trenches 1004. Thus, the conductive material 1800 corresponds to read bitlines (e.g., 116 in FIG. 1). In some embodiments, the conductive material 1800 is formed by a physical deposition process, such as sputtering, electroplating, atomic layer deposition, or physical vapor deposition. In some embodiments, the conductive material 1800 is a metal, and can comprise tungsten because of tungsten's good fill properties and affinity for filling small gaps without forming voids.

[0047] In FIG. 19, a third mask (not shown), such as a photomask is patterned over the uppermost memory stack, and a wet or dry etch is carried out with the third mask in place to re-open the WWL trenches 1004 by removing the conductive material 1800 from those WWL trenches 1004 while the conductive material 1800 remains in the RBL trenches. The wet etch or dry etch can proceed down to the substrate 202.

[0048] In FIG. 20, a fourth lateral etch is carried out to remove outermost portions of the oxide layer 222, a gate dielectric layer 208, and capacitor dielectric layer 212 nearest the WWL trenches 1004, thereby forming recesses 2002 in outer edges of the WWL trenches. In some embodiments, this fourth lateral etch is a wet etch or a dry etch and comprises fluorine. In some embodiments, the fourth etch is based on remote plasma process including two main steps referred to as an etch step and an anneal step. During the etch step of the two main steps, fluorosilicate salts are generated on the wafer through the reaction of NH4F reactive species with the outermost portions of the oxide layer 222. Then, during the anneal step of the two main steps, the fluorsilicate salts sublimate to permit the selective etching of the oxide layer 222 over the substrate 202 and further dielectric regions 224 and 226 (e.g., nitride).

[0049] In FIG. 21, a conductive material 2100 is deposited to fill in the re-opened WWL trenches 1004 and to fill in the corresponding recesses 2002 of FIG. 20. In some embodiments, the conductive material 2100 is formed by a physical deposition process, such as sputtering, electroplating, atomic layer deposition, or physical vapor deposition. In some embodiments, the conductive material 2100 is a metal, and can comprise tungsten because of tungsten's low resistivity, good fill properties, and affinity for filling small gaps without forming voids. The conductive material 2100 can be the same composition or a different composition from the conductive material 1800 depending on the implementation.

[0050] In FIG. 22, a fourth mask (not shown) is formed and a vertical etch is performed with the fourth mask in place to re-open the WWL trenches 1004 while leaving regions of the conductive material 2100 in place along sidewalls of the memory stacks nearest the WWL tranches 1004. The fourth mask covers the conductive material 1800 such that the conductive material 1800 is left in the RBL trenches.

[0051] In FIG. 23, a fifth lateral etch is carried out to remove outermost portions of the conductive material 2100 nearest the WWL trenches, thereby forming recesses 2302 in outer edges of the WWL trenches 1004. In some embodiments, this fifth lateral etch is a wet etch or a dry etch and comprises fluorine.

[0052] In FIG. 24 a dielectric is formed to entirely or partially fill the re-opened WLL trenches 1004 and the corresponding recesses 2302. The dielectric can comprise silicon dioxide in some embodiments, but can also be a low-k dielectric in other embodiments. After the dielectric is formed to fill the re-opened WLL 1004 trenches and the corresponding recesses, a vertical etch is performed to re-open the WWL trenches, while leaving dielectric material 2400 in the corresponding recesses.

[0053] In FIG. 25, a high-k material 2500 is formed over the structure. In some embodiments, the high-k material is a conformal dielectric that lines bottom surfaces and sidewalls of the WWL trenches 1004 and extends over the top surfaces of the structure.

[0054] In FIG. 26, a high-k material is etched back, for example using a vertical etch such as a dry etch to remove the lateral portions of the high-k material while leaving the high-k material 2602 on sidewalls of the WWL trenches 1004.

[0055] In FIG. 27, a conductive material 2700 is deposited to fill in the re-opened WWL trenches 1004 over the high-k material 2602. In some embodiments, the conductive material 2700 is formed by a physical deposition process, such as sputtering, electroplating, atomic layer deposition, or physical vapor deposition. In some embodiments, the conductive material 2700 is a metal, and can comprise tungsten because of tungsten's good fill properties and affinity for filling small gaps without forming voids. A CMP may be performed after conductive material 2700 is formed so upper surface of conductive material 2700 is planarized with the upper surface of isolation layer 224/226.

[0056] In FIG. 28, a cell isolation process is performed to form shafts 2802 to isolate the WWLs 110 of the various memory cells from one another. Thus, in FIG. 28, a fifth mask (not shown) is formed, and with the fifth mask in place, an etch is performed to form the shafts 2802 that segment the conductive material 2700 into separate WWLs 110 as shown.

[0057] In FIG. 29, columnar dielectric regions 2900 are formed to entirely or partially fill the shafts. The columnar dielectric regions 2900 can comprise silicon dioxide in some embodiments, but can also be a low-k dielectric in other embodiments. After the columnar dielectric regions are formed a CMP process is performed to planarize the upper surface of the structure.

[0058] FIG. 30 illustrates a methodology 3000 of forming a memory device in accordance with some embodiments. Although this method and other methods illustrated and/or described herein are illustrated as a series of acts or events, it will be appreciated that the present disclosure is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included.

[0059] In act 3002, multiple memory stacks are formed over a semiconductor substrate. Each memory stack includes a lower dielectric isolation layer, an oxide layer over the lower dielectric isolation layer, a gate dielectric layer over the oxide layer, a body layer over the gate dielectric layer, a capacitor dielectric layer over the body layer, an upper capacitor metal layer over the capacitor dielectric layer, and an upper dielectric isolation layer over the upper capacitor metal layer (wherein the upper dielectric isolation layer may be merged with or one in the same as the lower dielectric isolation layer for higher memory stacks). Thus, some embodiments of act 3002 correspond, for example to FIG. 9.

[0060] In act 3004, wet or dry etch is carried out with to form columns of patterned memory stack structures that are separated from one another by alternating RBL trenches and WWL trenches. Thus, some embodiments of act 3004 correspond, for example to FIG. 10.

[0061] In act 3006, a first lateral etch is performed to remove outermost portions of the upper capacitor metal layer in each memory stack structure, thereby forming recesses in sidewalls of the patterned memory stack structures. Thus, some embodiments of act 3006 correspond, for example to FIG. 11.

[0062] In act 3008, the RBL trenches and the WWL trenches between patterned columns of memory stack structures are filled with dielectric material. Thus, some embodiments of act 3008 correspond, for example to FIG. 12.

[0063] In act 3010, the RBL trenches are re-opened while the dielectric material is left in the WWL trenches. Thus, some embodiments of act 3010 correspond, for example to FIG. 13.

[0064] In act 3012, a second lateral etch is performed to remove outermost portions of oxide layers of the memory stacks, thereby forming recesses in outer edges of the memory stack columns. Thus, some embodiments of act 3012 correspond, for example to FIG. 14.

[0065] In act 3014, conductive read word line (RWL) is formed adjacent to the RBL trenches and is separated from the RBL trenches by a dielectric material. Thus, some embodiments of act 3014 correspond, for example, to FIGS. 15-17.

[0066] In act 3016, a conductive material is formed to establish conductive read bit lines (RBLs) in the RBL trenches, and sacrificial write wordlines (WWLs) in the WWL trenches. Thus, some embodiments of act 3016 correspond, for example, to FIG. 18.

[0067] In act 3018, the WBL trenches are re-opened while the RBLs are left in the RBL trenches. Thus, some embodiments of act 3018 correspond, for example to FIG. 19.

[0068] In act 3020, a third lateral etch is performed to remove outermost portions of capacitor dielectric regions, gate dielectric regions, and oxide regions of the memory stacks, thereby forming recesses in outer edges of the memory stack columns. Thus, some embodiments of act 3020 correspond, for example to FIG. 20.

[0069] In act 3022, a conductive write bitline (WBL) is formed adjacent to the WWL trenches and is separated from the WWL trenches by a dielectric material. Thus, some embodiments of act 3022 correspond, for example, to FIGS. 21-24.

[0070] In act 3024, a high-k gate dielectric is formed over an upper surface of the memory stack regions, along sidewalls of the memory stack regions, and over an exposed upper surface of the semiconductor substrate between the memory stack regions. Thus, some embodiments of act 1718 correspond, for example to FIG. 25.

[0071] In act 3026, the high-k gate dielectric is etched back, and a conductive material is formed in the WWL trenches. Thus, some embodiments of act 3026 correspond, for example to FIGS. 26-27.

[0072] In act 3028, a cell isolation process is performed to form shafts to segment the conductive material in the WWL trenches to form WWLs that are isolated from one another; and columnar dielectric regions are formed to entirely or partially fill the shafts. Thus, some embodiments of act 3028 correspond, for example to FIGS. 28-29.

[0073] Thus, some embodiments relate to a memory device that includes a plurality of memory cells. A first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. A first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. The first read source is coupled to the first write source. A first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor.

[0074] Other embodiments relate to a semiconductor memory structure disposed on a semiconductor substrate. A first body region is disposed over an upper surface of the semiconductor substrate, and a first write wordline extends along a first side of the first body region. The write wordline is separated from the first side of the first body region by a first write wordline gate dielectric. A first read bitline extends along a second side of the first body region opposite the first side and is coupled to the first body region. A first write bitline is disposed between the upper surface of the semiconductor substrate and a lower surface of the first body region, and is disposed between the first write wordline and the first read bitline. A first read wordline is disposed between the upper surface of the semiconductor substrate and the lower surface of the first body region, and is disposed between the first write bitline and the first read bitline. The first read wordline is separated from the lower surface of the first body region by a first read wordline gate dielectric; and a first capacitive element is disposed over an upper surface of the first body region and disposed between the first write wordline and the first read bitline. The first capacitive element is configured to selectively store varying levels of charge corresponding to varying data states on the first body region.

[0075] Some embodiments relate to a method. In the method, multiple memory stacks are stacked over one another and are stacked over a semiconductor substrate. An etch is performed to pattern the memory stacks into multiple columns of memory stack structures, wherein read bitline (RBL) trenches and write wordline (WWL) trenches are on opposite sides of the columns of multiple columns of memory stack structures to separate the multiple columns of memory stack structures from one another. A first lateral etch is performed to remove outermost conductive regions from each memory stack structure, thereby forming first recesses in sidewalls of each memory stack structure. The RBL trenches, the WWL trenches, and the first recesses are filled with dielectric material. The RBL trenches are re-opened while the WWL trenches are left filled with the dielectric material.

[0076] The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.