A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.

Methods for processing of a workpiece are disclosed. A fluid that contains a desired dopant is prepared. The workpiece is immersed in this fluid, such that the dopant is able to contact all surfaces of the workpiece. The fluid is then evacuated, leaving behind the dopant on the workpiece. The dopant is then subjected to a thermal treatment to drive the dopant into the surfaces of the workpiece. In certain embodiments, a selective doping process may be performed by applying a mask to certain surfaces prior to immersing the workpiece in the fluid. In certain embodiments, the fluid may be in a super-critical state to maximize the contact between the dopant and the workpiece.

A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.

A semiconductor device includes a first FinFET device and a second FinFET device. The first FinFET device includes a first gate, a first source, and a first drain. The first FinFET device has a first source/drain proximity. The second FinFET device includes a second gate, a second source, and a second drain. The second FinFET device has a second source/drain proximity that is smaller than the first source/drain proximity. In some embodiments, \the first FinFET device is an Input/Output (I/O) device, and the second FinFET device is a non-I/O device such as a core device. In some embodiments, the greater source/drain proximity of the first FinFET device is due to an extra spacer of the first FinFET device that does not exist for the second FinFET device.

Embodiments of the present disclosure relate to precision material modification of three dimensional (3D) features or advanced processing techniques. Directional ion implantation methods are utilized to selectively modify desired regions of a material layer to improve etch characteristics of the modified material. For example, a modified region of a material layer may exhibit improved etch selectivity relative to an unmodified region of the material layer. Methods described herein are useful for manufacturing 3D hardmasks which may be advantageously utilized in various integration schemes, such as fin isolation and gate-all-around, among others. Multiple directional ion implantation processes may also be utilized to form dopant gradient profiles within a modified layer to further influence etching processes.

A FinFET includes a substrate, a plurality of insulators disposed on the substrate, a gate stack and a strained material. The substrate includes at least one semiconductor fin and the semiconductor fin includes at least one modulation portion distributed therein. The semiconductor fin is sandwiched by the insulators. The gate stack is disposed over portions of the semiconductor fin and over portions of the insulators. The strained material covers portions of the semiconductor fin that are revealed by the gate stack. In addition, a method for fabricating the FinFET is provided.

The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion.

A method of making a semiconductor structure is provided including providing a plurality of fins on a semiconductor substrate; depositing a layer containing silicon dioxide on the plurality of fins and on a surface of the semiconductor substrate; depositing a photoresist layer on one or more but less than all of the plurality of fins; etching the layer of silicon dioxide off of one or more of the plurality of fins on which the photoresist layer had not been deposited; stripping the photoresist layer; depositing a layer of pure boron on one or more of the plurality of fins on which a photoresist had not been deposited; and depositing a silicon nitride liner step on the plurality of fins. A partial semiconductor device fabricated by said method is also provided.

A method for doping fins includes depositing a first dopant layer at a base of fins formed in a substrate, depositing a dielectric layer on the first dopant layer and etching the dielectric layer and the first dopant layer in a first region to expose the substrate and the fins. A second dopant layer is conformally deposited over the fins and the substrate in the first region. The second dopant layer is recessed to a height on the fins in the first region. An anneal is performed to drive dopants into the fins from the first dopant layer in a second region and from the second dopant layer in the first region to concurrently form punch through stoppers in the fins and wells in the substrate.

A method for doping fins includes depositing a first dopant layer at a base of fins formed in a substrate, depositing a dielectric layer on the first dopant layer and etching the dielectric layer and the first dopant layer in a first region to expose the substrate and the fins. A second dopant layer is conformally deposited over the fins and the substrate in the first region. The second dopant layer is recessed to a height on the fins in the first region. An anneal is performed to drive dopants into the fins from the first dopant layer in a second region and from the second dopant layer in the first region to concurrently form punch through stoppers in the fins and wells in the substrate.