A semiconductor device including an insulating film in a first region of a semiconductor substrate; a first impurity region and a second impurity region of a first conductivity type, each of the regions including a part located deeper than the insulating film in contact with each other, and the insulating film being sandwiched by the first and second impurity regions in planar view in the first region of the semiconductor substrate; a metal silicide film on the first impurity region and in Schottky junction with the first impurity region; a first impurity of the first impurity region having a peak of a concentration profile deeper than a bottom of the insulating film; a second impurity of the second impurity region having a concentration higher than a concentration of the first impurity in a part of the first impurity region shallower than the bottom of the insulating film.

A Tunnel Field-Effect Transistor comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region doped with a dopant element having a first dopant type and a first doping concentration; a drain region doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region situated between the source region and the drain region and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel region and extending at the source side up to at least an interface between the source region and the channel region, a drain extension region in the channel region or on top thereof, the drain extension region being formed from a material suitable for creating, and having a length/thickness ratio such that, in use, it creates a charged layer, in the OFF-state of the TFET, with a charge opposite to the charge of the majority carriers in the drain region.

A semiconductor device and a fabrication method are provided. The semiconductor device is fabricated by providing a substrate with a device area surrounded by a seal ring area, forming a buried deep-well layer in the substrate of the seal ring area, forming a first well region and a second well region in the substrate above the buried deep-well layer with the first well region surrounding the device area and the second well region surrounding the first well region, forming a heavily doped region in the substrate above the buried deep-well layer and between the first well region and the second well region, and forming a seal ring structure connecting to the heavily doped region. The buried deep-well layer, the first well region, and the second well region all have a first doping type while the heavily doped region and the substrate have a second doping type.

A III-nitride structure can include a silicon substrate, a nucleation layer over the silicon substrate, and a carbon-doped buffer layer over the nucleation layer. The carbon-doped buffer layer can include a III-nitride material and a concentration of carbon that is greater than 110.sup.20 cm.sup.3. The III-nitride structure can include a III-nitride channel layer over the carbon-doped buffer layer and a III-nitride barrier layer over the III-nitride channel layer. The carbon doping to a carbon concentration greater than 110.sup.20 cm.sup.3 can increase the compressive stress in the III-nitride structure.

Well-controlled, conformal doping of semiconductor substrates may be achieved by low temperature hydrogen-containing plasma treatment prior to gas phase doping. Substrates doped in this manner may be capped and annealed for thermal drive-in of the dopant. The technique is particularly applicable to the formation of ultrashallow junctions (USJs) in three-dimensional (3D) semiconductor structures, such as FinFET and Gate-All-Around (GAA) devices.

A semiconductor device and a manufacturing method thereof is disclosed in which the semiconductor device includes a p-type anode layer formed by a transition metal acceptor transition, and the manufacturing process is significantly simplified without the breakdown voltage characteristics deteriorating. An inversion advancement region inverted to a p-type by a transition metal acceptor transition, and in which the acceptor transition is advanced by point defect layers, is formed on the upper surface of an n-type drift layer. The inversion advancement region configures a p-type anode layer of a semiconductor device of the invention. The transition metal is, for example, platinum or gold. An n-type semiconductor substrate with a concentration higher than that of the n-type drift layer is adjacent to the lower surface of the n-type drift layer.

An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

A simplified manufacturing process stably produces a semiconductor device with high electrical characteristics, wherein platinum acts as an acceptor. Plasma treatment damages the surface of an oxide film formed on a n.sup. type drift layer deposited on an n.sup.+ type semiconductor substrate. The oxide film is patterned to have tapered ends. Two proton irradiations are carried out on the n.sup. type drift layer with the oxide film as a mask to form a point defect region in the vicinity of the surface of the n.sup. type drift layer. Silica paste containing 1% by weight platinum is applied to an exposed region of the n.sup. type drift layer surface not covered with the oxide film. Heat treatment inverts the vicinity of the surface of the n.sup. type drift layer to p-type by platinum atoms which are acceptors. A p-type inversion enhancement region forms a p-type anode region.

A fin field effect transistor (FinFET) and a method of forming the same are introduced. In an embodiment, trenches are formed in a substrate, wherein a region between adjacent trenches defines a fin. A dielectric material is formed in the trenches. A part of the substrate is doped and a region of high dopant concentration and a region of low dopant concentration are formed. Gate stacks are formed, portions of the fins are removed and source/drain regions are epitaxially grown in the regions of high/low dopant concentration. Contacts are formed to provide electrical contacts to source/gate/drain regions.

A semiconductor device includes an IGBT region with a bottom-body region on a front surface side of an IGBT drift region, an IGBT barrier region on a front surface side of the bottom-body region, and a top-body region on a front surface side of the IGBT barrier region. A diode region is include with a bottom-anode region on a front surface side of the diode drift region, a diode barrier region on a front surface side of the bottom-anode region, a top-anode region on a front surface side of the diode barrier region, and a pillar region extending from the front surface of the semiconductor substrate, piercing the top-anode region, and reaching the diode barrier region, and connected to the front surface electrode and the diode barrier region. An impurity concentration of the top-body region is lower than an impurity concentration of the bottom-anode region.