A semiconductor device includes a substrate having an upper surface layer of a second conduction type formed at an upper surface side, a drift layer of a first conduction type formed under the upper surface layer, a buffer layer of the first conduction type formed under the drift layer, and a lower surface layer of the second conduction type formed under the buffer layer, the buffer layer includes a plurality of upper buffer layers provided apart from each other, and a plurality of lower buffer layers provided apart from each other between the plurality of upper buffer layers and the lower surface layer, wherein the plurality of upper buffer layers are formed so that average impurity concentrations in first sections each extending from the upper end of one of the upper buffer layers to the next lower buffer layer are unified as a first concentration.

In one example, a method of compensating resistance in an integrated circuit includes providing a four terminal resistor in a semiconductor substrate. The resistor includes a first resistor and a second resistor coupled in series, a first terminal at a first end of the resistor, a second terminal at a second end of the resistor, a test terminal at a node connecting the first resistor and the second resistor, and a tuning terminal. The first resistor has a first conductivity type and the second resistor has a second conductivity type opposite to the first conductivity type. The first resistor includes a first portion extending along a first direction and a second portion extending along a second direction perpendicular to the first direction. The method further includes computing a voltage to be applied at the tuning terminal to compensate the difference between the resistance of the first and the second resistors.

A semiconductor device includes a trench formed in an epitaxial layer and an oxide layer that lines the sidewalls of the trench. The thickness of the oxide layer is non-uniform, so that the thickness of the oxide layer toward the top of the trench is thinner than it is toward the bottom of the trench. The epitaxial layer can have a non-uniform dopant concentration, where the dopant concentration varies according to the thickness of the oxide layer.

A high-voltage semiconductor structure including a substrate, a first doped region, a well, a second doped region, a third doped region, a fourth doped region, and a gate structure is provided. The substrate has a first conductive type. The first doped region has the first conductive type and is formed in the substrate. The well has a second conductive type and is formed in the substrate. The second doped region has the second conductive type and is formed in the first doped region. The third doped region has the first conductive type and is formed in the well. The fourth doped region has the second conductive type and is formed in the well. The gate structure is disposed over the substrate and partially covers the first doped region and the well.

A semiconductor device includes a plurality of compensation regions of a vertical electrical element arrangement, a plurality of drift regions of the vertical electrical element arrangement and a non-depletable doping region. The compensation regions of the plurality of compensation regions are arranged in a semiconductor substrate of the semiconductor device. Further, the plurality of drift regions of the vertical electrical element arrangement are arranged in the semiconductor substrate within a cell region of the semiconductor device. The plurality of drift regions and the plurality of compensation regions are arranged alternatingly in a lateral direction. The non-depletable doping region extends laterally from an edge of the cell region towards an edge of the semiconductor substrate. The non-depletable doping region has a doping non-depletable by voltages applied to the semiconductor device during blocking operation.

One aspect of this disclosure is a power amplifier module that includes a power amplifier die, a first bonding pad on a conductive trace, and a second bonding pad on a conductive trace. The die includes an on-die passive device and a power amplifier. The first bonding pad is electrically connected to the on-die passive device by a first wire bond. The second bonding pad is in a conductive path between the first bonding pad and a radio frequency output of the power amplifier module. The second bonding pad includes a nickel layer having a thickness that is less than 0.5 um, a palladium layer over the nickel layer, and a gold layer over the palladium layer and bonded to a second wire bond that is electrically connected to an output of the power amplifier. Other embodiments of the module are provided along with related methods and components thereof.

There is provided an MPS diode comprising a first semiconductor layer that is an N type; P-type semiconductor regions and N-type semiconductor regions that are arranged alternately on one surface of the first semiconductor layer; and a Schottky electrode that is in Schottky junction with the N-type semiconductor regions and is arranged to be adjacent to and in contact with at least part of the P-type semiconductor regions. A donor concentration in an area of the N-type semiconductor region that is adjacent to and in contact with the first semiconductor layer is lower than the donor concentration in an area of the first semiconductor layer that is adjacent to and in contact with the N-type semiconductor region and is lower than the donor concentration in an area of the N-type semiconductor region that is adjacent to and in contact with the Schottky electrode. This configuration improves a breakdown voltage under applying a reverse bias voltage and reduces a rising voltage under applying a forward bias voltage.

A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.410.sup.17 cm.sup.3 or higher and 610.sup.17 cm.sup.3 or lower and an impurity concentration in a second JTE region is set to 210.sup.17 cm.sup.3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 610.sup.17 cm.sup.3 or higher and 810.sup.17 cm.sup.3 or lower and an impurity concentration in the second JTE region is set to 210.sup.17 cm.sup.3 or lower in a case of a junction barrier Schottky diode.

One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to amplify a radio frequency (RF) signal and tantalum nitride terminated through wafer via. The power amplifier includes a heterojunction bipolar transistor and a p-type field effect transistor, in which a semiconductor portion of the p-type field effect transistor corresponds to a channel includes the same type of semiconductor material as a collector layer of the heterojunction bipolar transistor. A metal layer in the tantalum nitride terminated through wafer via is included in an electrical connection between the power amplifier on a front side of a substrate and a conductive layer on a back side of the substrate. Other embodiments of the module are provided along with related methods and components thereof.

A Magnetic Czochralski semiconductor wafer having opposing first and second sides arranged distant from one another in a first vertical direction is treated by implanting first particles into the semiconductor wafer via the second side to form crystal defects in the semiconductor wafer. The crystal defects have a maximum defect concentration at a first depth. The semiconductor wafer is heated in a first thermal process to form radiation induced donors. Implantation energy and dose are chosen such that the semiconductor wafer has, after the first thermal process, an n-doped semiconductor region arranged between the second side and first depth, and the n-doped semiconductor region has, in the first vertical direction, a local maximum of a net doping concentration between the first depth and second side and a local minimum of the net doping concentration between the first depth and first maximum.