Semiconductor device with substantially equal impurity concentration JTE regions in a vicinity of a junction depth

Abstract

A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.410.sup.17 cm.sup.3 or higher and 610.sup.17 cm.sup.3 or lower and an impurity concentration in a second JTE region is set to 210.sup.17 cm.sup.3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 610.sup.17 cm.sup.3 or higher and 810.sup.17 cm.sup.3 or lower and an impurity concentration in the second JTE region is set to 210.sup.17 cm.sup.3 or lower in a case of a junction barrier Schottky diode.

Claims

1. A semiconductor device comprising: a hollow annular p-type JTE region disposed on a drift region having an n-type conductivity, wherein the annular p-type JTE region includes a first JTE region and a second JTE region each having a substantially equal impurity concentration in a vicinity of a substantially same junction depth, wherein the first JTE region is disposed so as to be sandwiched between portions of the second JTE region, and wherein a p-type semiconductor region is formed adjacent to an innermost portion of the annular p-type JTE region.

2. The semiconductor device according to claim 1, wherein a difference in impurity concentration between the first JTE region and the second JTE region at a p-n junction depth is substantially zero.

3. The semiconductor device according to claim 1, wherein a ratio between a width and a space of the second JTE region decreases in accordance with a distance from the p-type semiconductor region.

4. The semiconductor device according to claim 1, wherein the p-type semiconductor region has a junction depth deeper than a junction depth in the annular p-type JTE region.

5. The semiconductor device according to claim 1, wherein an impurity concentration in the first JTE region is set to 4.410.sup.17 cm.sup.3 or higher and 810.sup.17 cm.sup.3 or lower and an impurity concentration in the second JTE region is set to 210.sup.17 cm.sup.3 or lower.

6. The semiconductor device according to claim 1, wherein a field intensity of a protective insulation film at an outermost peripheral position of the second JTE region does not exceed 2 MV/cm.

Description

BRIEF DESCRIPTIONS OF THE DRAWINGS

(1) FIG. 1 is a plan view illustrating a semiconductor device according to a first embodiment;

(2) FIG. 2 is a sectional view illustrating the semiconductor device according to the first embodiment;

(3) FIG. 3 is a plan view illustrating a semiconductor device according to a second embodiment;

(4) FIG. 4 is a sectional view illustrating the semiconductor device according to the second embodiment;

(5) FIG. 5 is a graph illustrating a concentration distribution of Al in a depth direction in a JTE region of the semiconductor device according to the first embodiment and the second embodiment;

(6) FIG. 6 is a graph illustrating a concentration distribution of Al in a depth direction in a JTE region of a semiconductor device according to the first embodiment and the second embodiment;

(7) FIG. 7 is a graph illustrating a concentration distribution of Al in a depth direction according to a comparative example; and

(8) FIG. 8 is a sectional view illustrating a semiconductor device according to the comparative example.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(9) Embodiments of the present invention will be described below.

First Embodiment

(10) FIG. 1 is a plan view illustrating a semiconductor device (protective films and others are omitted) according to the first embodiment, and FIG. 2 is a sectional view of the semiconductor device.

(11) The semiconductor device according to the first embodiment is a Schottky diode having an SiC substrate. This semiconductor device includes a drift layer 2 which is an n-type semiconductor region formed on a semiconductor substrate 1 by epitaxial growth, a Schottky electrode 10 formed in a main junction region disposed on an upper surface of the drift layer 2, a p-type semiconductor region 3 implanted with a p-type impurity such as Al and formed as a guard ring around the Schottky electrode 10, and a cathode electrode 4 formed on a rear surface of the semiconductor substrate 1. Further, the semiconductor device includes a JTE (Junction Termination Extension) region 6 constituted of an annular p-type semiconductor region so as to surround the main junction region.

(12) The semiconductor substrate 1 is an n.sup.+-type semiconductor substrate which is mainly composed of SiC to which an n-type impurity such as N is implanted at a high concentration.

(13) The drift layer is an n.sup.-type semiconductor layer which is mainly composed of SiC to which an n-type impurity such as N is implanted. The impurity concentration thereof is lower than that of the semiconductor substrate 1.

(14) The JTE region 6 is made up of high impurity density regions (first JTE regions) 7 and low impurity density regions (second JTE regions) 8, and a ratio between width and space of the second JTE regions gradually decreases in a direction from the main junction 3 toward outside.

(15) In the first embodiment, the first JTE region and the second JTE region are formed by multi-stage Al ion implantation using the following ion implantation energies.

(16) First ion implantation energy (first JTE region): 25, 55, 95, 150, 220 and 320 keV.

(17) Second ion implantation energy (first JTE region and second JTE region): 25, 55, 95, 150, 220, 320 and 450 keV.

(18) The maximum Al concentration (peak setting concentration in box profile) in the first JTE region is set to 610.sup.17 cm.sup.3 and the maximum Al concentration of the second JTE region is set to 210.sup.17 cm.sup.3, but by making the highest ion implantation energy to a highly doped region (first ion implantation energy) lower than the second ion implantation energy, the difference in concentration between the two regions of the first JTE region and the second JTE region in a horizontal direction at the p-n junction depth becomes almost zero as illustrated by the Al concentration distribution in FIG. 5.

(19) As a comparative example, FIG. 7 illustrates an Al concentration distribution in a depth direction in the case where the first ion implantation and the second ion implantation are performed with the same implantation energy like the Non-Patent Document 1. In this example, a large discontinuity occurs in the Al concentration distribution in the horizontal direction (substrate in-plane direction) at a depth (depth of 0.7 to 0.9 m) of a p-n junction formed between the drift layer 2 and the JTE region 6. In particular, unlike the case where the ion implantation energy is set to be as high as 700 keV of the Non-Patent Document 1, when the ion implantation energy is equal to or lower than 450 keV, the Al ion channeling cannot be ignored as disclosed in the Non-Patent Document 3. Specifically, if the Al ion implantation of the first JTE region and the second JTE region is carried out with an implantation dose ratio of 3 to 1 between the first JTE region and the second JTE region like the Non-Patent Document 1 and with the same multi-stage energy having the maximum value of 450 keV or less, the Al concentration sustains its state even at the depth of 0.6 m or more in a graph of the Al concentration distribution in the depth direction as illustrated in FIG. 7. As a result, the diode having the structure illustrated in FIG. 8 can only acquire the actual withstand voltage of no more than about 70% relative to the ideal withstand voltage in the case where the diode has an infinite size, namely, in the case where there is no peripheral region and the diode can be regarded as one-dimensional structure in the vertical direction.

(20) In contrast, the diode manufactured according to the first embodiment illustrated in FIG. 1 has a withstand voltage that exceeds 90% of the ideal withstand voltage in the case where the diode has an infinite size. This is assumed to be because the concentration setting of the first JTE region and the second JTE region is adjusted and the difference in concentration between the two regions of the first JTE region and the second JTE region in a horizontal direction at the p-n junction depth is made almost zero, so that an electric field is less likely to be concentrated on a boundary between the first JTE region and the second JTE region.

(21) Also, with the maximum Al concentration (peak setting concentration in box profile) in the JTE region of the first embodiment, the field intensity of a protective insulating film (not illustrated in FIG. 2) at the outermost peripheral position of the second JTE region does not exceed 2 MV/cm, and thus the problem of the breakage of the insulating film does not occur in the measurement of initial characteristics.

(22) Furthermore, as a result of the measurement in which the diode was retained at 125 C. for 1000 hours in the state of setting the reverse voltage to 80% of the rated withstand voltage and was then cooled to a room temperature while applying the reverse voltage, the breakage of the Schottky diode by the application of the voltage equal to or lower than an initial withstand voltage was not found at all. This is assumed to be because the maximum concentration of the first JTE region is high and the withstand voltage is thus not deteriorated even under the severe test condition in which the interfacial charge density exceeds 710.sup.12 cm.sup.2.

(23) Also, when the maximum Al concentration in the first JTE region was set to 410.sup.17 cm.sup.3 and the maximum Al concentration in the second JTE region was set to 210.sup.17 cm.sup.3, the withstand voltage of the Schottky diode exceeded 90% of the ideal withstand voltage. However, as a result of the measurement in which the diode was retained at 125 C. for 1000 hours in the state of setting the reverse voltage to 80% of the rated withstand voltage and was then cooled to a room temperature while applying the reverse voltage, the breakage of the Schottky diode by the application of the voltage equal to or lower than an initial withstand voltage was found. The presence of positive charge at the density of about 110.sup.12 cm.sup.2 to 210.sup.12 cm.sup.2 at an Interface between an insulating film and the semiconductor in an initial state has been known in the case of a semiconductor device using SiC, and it is presumed that the interfacial charge varies toward the positive larger value during the test and this reduces the withstand voltage, which causes the breakage of the Schottky diode. When the maximum Al concentration in the first JTE region was set to 610.sup.17 cm.sup.3 and the maximum Al concentration in the second JTE region was set to 210.sup.17 cm.sup.3 like the first embodiment, the breakage of the Schottky diode was not found at all. Then, another test in which the maximum Al concentration in the first JTE region was increased from 4.010.sup.17 cm.sup.3 to 410.sup.16 cm.sup.3 in a step-by-step manner while fixing the maximum Al concentration in the second JTE region at 210.sup.17 cm.sup.3 was carried out. As a result of the test, it was found that the breakage of the Schottky diode did not occur when the maximum Al concentration in the first JTE region was equal to or higher than 4.410.sup.17 cm.sup.3. Furthermore, it was also found that the initial withstand voltage itself was decreased when the maximum Al concentration in the first JTE region was increased to 8.410.sup.17 cm.sup.3. Accordingly, in order to achieve a Schottky diode as a semiconductor device with high reliability, the range of the maximum concentration of the first JTE region is desirably from 4.410.sup.17 cm.sup.3 to 810.sup.17 cm.sup.3.

(24) As described above, according to the first embodiment, it is possible to enhance a withstand voltage of a semiconductor device such as a Schottky diode using SiC, and achieve the semiconductor device with high reliability.

Second Embodiment

(25) FIG. 3 is a plan view of a semiconductor device according to the second embodiment, and FIG. 4 is a sectional view of the semiconductor device.

(26) The major difference from the first embodiment lies in the point that the first JTE regions are disposed discretely under the Schottky electrode 10 and annularly around the Schottky electrode instead of the p-type semiconductor region 3 used as a guard ring, thereby forming a JBS diode. The implantation energy of the first JTE region and the second JTE region is the same as the first embodiment, and the implantation dose of the first JTE region is controlled so that the maximum Al concentration in the first JTE region has three values such as 4.410.sup.17 cm.sup.3 (not illustrated), 610.sup.17 cm.sup.3 (FIG. 5) and 810.sup.17 cm.sup.3 (FIG. 6) and the implantation dose of the second JTE region is controlled so that the maximum Al concentration in the second JTE region becomes 210.sup.17 cm.sup.3 (FIG. 5 and FIG. 6).

(27) In the JBS diode manufactured according to the second embodiment, when the maximum Al concentration in the first JTE region was 4.410.sup.17 cm.sup.3, the withstand voltage was decreased to 60% of the ideal withstand voltage in the case where the diode had an infinite size. This is assumed to be because the maximum Al concentration in the first JTE region of 4.410.sup.17 cm.sup.3 was too low for the substitute of the p-type semiconductor region 3 of the first embodiment. In contrast, when the maximum Al concentration in the first JTE region was 610.sup.17 cm.sup.3 and 810.sup.17 cm.sup.3, the withstand voltage exceeded 90% of the ideal withstand voltage in the case where the diode had an infinite size. Then, when the maximum Al concentration in the first JTE region was 610.sup.17 cm.sup.3 and 810.sup.17 cm.sup.3, the breakage of the JBS diode by the application of the voltage equal to or lower than an initial withstand voltage was not found at all in the measurement in which the diode was retained at 125 C. for 1000 hours in the state of setting the reverse voltage to 80% of the rated withstand voltage and was then cooled to a room temperature while applying the reverse voltage. Accordingly, in order to achieve a JBS diode as a semiconductor device with high reliability, the range of the maximum concentration of the first JTE region is desirably from 610.sup.17 cm.sup.3 to 810.sup.17 cm.sup.3.

(28) According to the second embodiment, it is possible to achieve a semiconductor device such as a JBS diode using SiC with high reliability and also possible to omit a process of forming the p-type semiconductor region 3 formed as a guard ring in the first embodiment, thereby reducing the manufacturing cost of the semiconductor device.

(29) In the foregoing, the invention made by the inventors of the present invention has been concretely described based on the embodiments. However, it is needless to say that the present invention is not limited to the foregoing embodiments and various modifications and alterations can be made within the scope of the present invention.

REFERENCE SIGNS LIST

(30) 1 semiconductor substrate 2 drift region 3 p-type semiconductor region 4 cathode electrode 6 JTE region 7 first JTE region with large implantation dose 8 second JTE region with small implantation dose 9 example of position of avalanche breakdown 10 Schottky electrode