The present invention relates to a capacitor and a method for manufacturing the same that can improve a dielectric property and a leakage current property of the capacitor by enabling the deposition of a crystalline dielectric film under a low process temperature of 500 C. or lower simultaneously with fundamentally blocking the generation of interfacial oxides when depositing oxides having a perovskite crystal structure through atomic layer deposition (ALD). The capacitor according to the present invention is characterized by comprising a lower electrode having a structure in which a platinum ultra-thin film layer is laminated on a ruthenium thin film layer; a dielectric film laminated on the platinum ultra-thin film layer; and an upper electrode laminated on the dielectric film.

A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

A deep trench structure may be formed between electrodes of a capacitive device. The deep trench structure may be formed to a depth, a width, and/or an aspect ratio that increases the volume of the deep trench structure relative to a trench structure formed using a metal etch-stop layer. Thus, the deep trench structure is capable of being filled with a greater amount of dielectric material, which increases the capacitance value of the capacitive device. Moreover, the parasitic capacitance of the capacitive device may be decreased by omitting the metal etch-stop layer. Accordingly, the deep trench structure (and the omission of the metal etch-stop layer) may increase the sensitivity of the capacitive device, may increase the humidity-sensing performance of the capacitive device, and/or may increase the performance of devices and/or integrated circuits in which the capacitive device is included.

An integrated circuit device includes: a lower electrode disposed on a substrate; an insulating support pattern supporting the lower electrode; a dielectric film surrounding the lower electrode and the insulating support pattern; a high-k interface layer arranged between the lower electrode and the dielectric film and between the insulating support pattern and the dielectric film, wherein the high-k interface layer contacts the insulating support pattern and includes a zirconium oxide layer; and an upper electrode disposed adjacent the lower electrode, wherein the high-k interface layer and the dielectric film are disposed between the upper electrode and the lower electrode.

In an aspect, an IC device may include a base substrate including an embedded component and a first metallization structure. The first metallization structure includes a plurality of first metal layers, a plurality of first dielectric layers, a plurality of first vias configured to couple adjacent metal layers of the plurality of first metal layers through the plurality of first dielectric layers and a reserve capacitor disposed within one of the plurality of first dielectric layers. The reserve capacitor directly coupled between a first contact pad and a second contact pad formed in one of the plurality of first metal layers, and electrically coupled to the embedded component.

Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

A capacitor according to an embodiment of the present disclosure includes a substrate, a first electrode disposed on the substrate, a dielectric film disposed on the first electrode, a second electrode disposed on the dielectric film, a third electrode in contact with the second electrode in a first region of at least a portion of a lower surface of the third electrode, and an organic insulator film covering an upper portion of the dielectric film, an upper portion of the second electrode, and the third electrode. In a normal direction normal to an upper surface of the substrate, the organic insulator film is not disposed between the lower surface of the third electrode and the second electrode.

A semiconductor device includes a semiconductor substrate, a first semiconductor layer on the semiconductor substrate, a second semiconductor layer on the first semiconductor layer, a first electrode on the second semiconductor layer, a second electrode arranged with the first electrode along a front surface of the second semiconductor layer, a third electrode between the first and second electrodes on the second semiconductor layer, a metal layer on a back surface of the semiconductor substrate at a side opposite to the first semiconductor layer, and a conductor extending inside the semiconductor substrate and electrically connecting the first electrode and the metal layer via the second semiconductor layer. The second semiconductor layer includes a first region including a first-conductivity-type impurity, and a second region including a first-conductivity-type impurity with a higher concentration than the first region; and the second region is between the conductor and the first electrode.

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a capacitor comprises a crystalline polar layer comprising a base polar material substitutionally doped with a dopant. The base polar material comprises one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element of one of 4d series, 5d series, 4f series or 5f series that is different from the one or more metal elements, such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV.

Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.