A deep trench structure may be formed between electrodes of a capacitive device. The deep trench structure may be formed to a depth, a width, and/or an aspect ratio that increases the volume of the deep trench structure relative to a trench structure formed using a metal etch-stop layer. Thus, the deep trench structure is capable of being filled with a greater amount of dielectric material, which increases the capacitance value of the capacitive device. Moreover, the parasitic capacitance of the capacitive device may be decreased by omitting the metal etch-stop layer. Accordingly, the deep trench structure (and the omission of the metal etch-stop layer) may increase the sensitivity of the capacitive device, may increase the humidity-sensing performance of the capacitive device, and/or may increase the performance of devices and/or integrated circuits in which the capacitive device is included.

A capacitor and a DRAM device, the capacitor including a lower electrode; a dielectric layer structure on the lower electrode, the dielectric layer structure including a first zirconium oxide layer, a hafnium oxide layer, and a second zirconium oxide layer sequentially stacked; and an upper electrode on the dielectric layer structure, wherein the hafnium oxide layer has a tetragonal crystal phase or an orthorhombic crystal phase.

A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

The present disclosure describes a semiconductor device having a ferroelectric memory with improved retention after cycling (RAC) memory window (MW) performance. The semiconductor device includes an interconnect structure on a substrate, a first electrode on the interconnect structure, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer. The first electrode includes a metal nitride conductive material having a nitrogen concentration greater than a metal concentration. The ferroelectric layer includes a ferroelectric material. The second electrode includes the metal nitride conductive material.

Provided is a semiconductor device. The semiconductor device includes a lower structure; a lower electrode on the lower structure; a dielectric layer on the lower electrode; and an upper electrode on the dielectric layer, wherein the lower electrode includes a bending reducing layer and a dielectric constant-increasing layer between the bending reducing layer and the dielectric layer, the dielectric constant-increasing layer is configured to increase a dielectric constant of the dielectric layer, and an elastic modulus of the bending reducing layer is greater than an elastic modulus of the dielectric constant-increasing layer.

A capacitor structure includes lower and electrodes, and a capacitor dielectric film interposed therebetween. The lower electrode includes a lower electrode film including a first metal element, a first doped oxide film including a second metal element and an oxide of the first metal element, and a first metal oxide film. The first metal oxide film includes an oxide of the first metal element and is free of the second metal element. The upper electrode includes an upper electrode film including the first metal element, a second doped oxide film including the second metal element and an oxide of the first metal element, and a second metal oxide film that includes an oxide of the first metal element, and is free of the second metal element.

Embodiments described herein may be related to apparatuses, processes, and techniques related to increasing the capacitance density of MIM capacitors on dies or within packages. In particular, a MIM stack is disclosed that has multiple insulator layers between the metal, in order to increase the dielectric constant of the MIM stack. In particular, the first dielectric layer may include strontium, titanium, and oxygen and may be physically coupled with a second dielectric layer that may include barium, strontium, titanium, and oxygen. Other embodiments may be described and/or claimed.

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

Landing metal layers with improved adhesion to semiconductor substrates are described, along with semiconductor structures including the landing metal layers and components using the landing metal layers. An example semiconductor device includes a substrate with top and bottom surfaces, a landing metal layer over the top surface of the substrate, a via that extends through the substrate, and a bottom side metal layer. The bottom side metal layer extends over sidewalls of the via and electrically contacts an underside of the landing metal layer. For improved adhesion, the landing metal layer is diffused at least in part into the top surface of the substrate. The landing metal layer is diffused into the top surface of the substrate by an annealing or alloying process, and the techniques described herein help to avoid the delamination of the landing metal layer from the top surface of the substrate.

A ferroelectric nanoparticle capacitor-device comprises a pair of conductive elements electrically insulated from each other, and ferroelectric nanoparticles arranged between the conductive elements of the pair. The ferroelectric nanoparticles are adapted to provide at least three polarization states with different total ferroelectric polarizations.