To improve accuracy and shielding capabilities of impurity implantation, a method of manufacturing a semiconductor device is provided, the method including forming a first photoresist on a front surface of a semiconductor substrate, the front surface being provided with a front surface structure, forming, on the first photoresist or below a rear surface of the semiconductor substrate, a second photoresist having opposite photo-curing properties from those of the first photoresist, and implanting impurities into the semiconductor substrate using as a mask the second photoresist, which has been subjected to patterning.

The present disclosure is to provide an optoelectronic device. The optoelectronic device comprises a heat dispersion substrate; an insulative protection layer on the heat dispersion substrate, wherein the insulative protection layer comprises AlInGaN series material; and an optoelectronic unit comprising an epitaxial structure comprising multiple layers on the insulative protection layer, wherein at least one layer of the epitaxial structure comprises III-V group material devoid of nitride.

A method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction (Z) perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction (Z), a drift layer having dopants of the first conductivity type above the back side emitter layer, wherein a dopant concentration of the back side emitter layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction (Zpn). Epitaxially growing the drift layer includes creating, within the drift layer, a dopant concentration profile (P) of dopants of the first conductivity type along the vertical direction (Z), the dopant concentration profile (P) in the drift layer exhibiting a variation of a concentration of dopants of the first conductivity type along the vertical direction (Z).

A chip resistor includes: a board having a device formation surface, a back surface opposite from the device formation surface and side surfaces connecting the device formation surface to the back surface, a resistor portion provided on the device formation surface, a first connection electrode and a second connection electrode provided on the device formation surface and electrically connected to the resistor portion, and a resin film covering the device formation surface with the first connection electrode and the second connection electrode being exposed therefrom. Intersection portions of the board along which the back surface intersects the side surfaces each have a rounded shape.

At least one method, apparatus and system disclosed involves an antenna diode design for a semiconductor device. A first common diode operatively coupled to a ground node and to a p-well layer serving as an isolated p-well that is formed over a deep n-well that is adjacent to an n-well in a semiconductor device is provided. A first antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a first signal line of the semiconductor device is provided for discharging accumulated charges on the first signal line. A second antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a second signal line of semiconductor device is provided for discharging accumulated charges on the second signal line.

A method for forming a semiconductor device includes implanting doping ions into a semiconductor substrate. A deviation between a main direction of a doping ion beam implanting the doping ions and a main crystal direction of the semiconductor substrate is less than 0.5 during the implanting of the doping ions into the semiconductor substrate. The method further includes controlling a temperature of the semiconductor substrate during the implantation of the doping ions so that the temperature of the semiconductor substrate is within a target temperature range for more than 70% of an implant process time used for implanting the doping ions. The target temperature range reaches from a lower target temperature limit to an upper target temperature limit. The lower target temperature limit is equal to a target temperature minus 30 C., and the target temperature is higher than 80 C.

In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.

A semiconductor device includes a semiconductor substrate with: a drift layer; a base layer; and a collector layer and a cathode layer. In the semiconductor substrate, when a region operating as an IGBT device is an IGBT region and a region operating as a diode device is a diode region, the IGBT and diode regions are arranged alternately in a repetitive manner; a damaged region is arranged on a surface portion of the diode region in the semiconductor substrate. The IGBT and diode regions are demarcated by a boundary between the collector and cathode layers; and a surface portion of the IGBT region includes: a portion having the damaged region at a boundary side with the diode region; and another portion without the damaged region arranged closer to an inner periphery side relative to the boundary side.

A manufacturing method includes an implantation of impurities and laser irradiation. In the implantation, impurities are implanted to first and second areas so as to obtain a relationship that a total amount of the first impurities is larger than a total amount of the second impurities in a first depth range and a total amount of the second impurities is larger than a total amount of the first impurities in a second depth range (deeper range). In the irradiation, the first and second areas are irradiated with laser so that an energy density of the laser is larger on the second area than on the first area. A first conductivity type region is formed on the first area so as to be exposed on the surface, and a second conductivity type region is formed on the second area so as to be exposed on the surface.

A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a central conductive layer, a silicon nitride layer, a metal diffusion layer, a channel region, and a metal sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. A silicon nitride layer is formed on the central conductive layer. A metal diffusion layer is formed within the guard ring and the central conductive layer. Afterwards, a metal sputtering layer is formed, and the mask layer is partially exposed.