A vertical III-nitride thin-film power diode can hold off high voltages (kV's) when operated under reverse bias. The III-nitride device layers can be grown on a wider bandgap template layer and growth substrate, which can be removed by laser lift-off of the epitaxial device layers grown thereon.

A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer.

An exemplary embodiment of the present disclosure provides a device, a substrate and a doped material. The doped material comprises a group III metal nitride, and one of a p-type dopant or an n-type dopant. The doped material is disposed upon the substrate at a temperature below 1000 C. and comprises an increased dopant concentration. Also disclosed herein are methods for producing doped group III metal nitride produces comprising flowing a plasma comprising nitrogen from a remote plasma chamber into a growth chamber; introducing a group III metal and at least one of a p-type dopant or an n-type dopant into the growth chamber; and disposing, over a substrate at a temperature below about 1000 C., a conductive group III metal nitride product comprising an increased electrical carrier concentration.

The monitoring device is configured for monitoring a converter comprising a first and a second input terminals, two output terminals, a first filter branch connected between the input terminals, a second filter branch connected in parallel with the first branch, two switching branches connected in parallel with the second branch, each switching branch including two switching half-branches connected in series and in an intermediate point forming an output terminal. The monitoring device comprises a detection impedance configured for being connected between the first and the second branches, and a detection module configured for comparing the voltage across the detection impedance with a predefined threshold, then for generating a detection signal as soon as said voltage is greater than said threshold.

A wide-band-gap diode and manufacturing method thereof are provided. The method of manufacturing a wide-band-gap diode involves growing an N-type doped epitaxial layer on an N-doped substrate. P-type ions are implanted into the epitaxial layer to form an active area, a junction termination extension region, and an edge region. The active area exhibits an axially symmetric graticule pattern, with higher doping area density towards the center of the active area. The junction termination extension region surrounds the active area, and the edge region encircles both of the active area and the junction termination extension region to enhance the wide-band-gap diode's capability to withstand surge currents.

A semiconductor device includes a semiconductor substrate that includes an IGBT region. A first lifetime control layer extending along a planar direction of the semiconductor substrate is provided in a range in a drift region that is closer to the rear surface than an intermediate portion of the semiconductor substrate in a thickness direction. A crystal defect density in the first lifetime control layer is higher than any of a crystal defect density in a region adjacent to the first lifetime control layer on the rear surface side and a crystal defect density in a region adjacent to the first lifetime control layer on a front surface side. A crystal defect density in a region between the first lifetime control layer and the rear surface is lower than a crystal defect density in a region between the first lifetime control layer and the front surface.

A semiconductor device, including a semiconductor substrate, a plurality of trenches formed on a front surface of the semiconductor substrate, a plurality of gate electrodes formed in the trenches, a base region and an anode region formed between adjacent trenches respectively in first and second element regions of the semiconductor substrate, a plurality of emitter regions and contact regions selectively formed in the base region, an interlayer insulating film covering the gate electrodes, first and second contact holes penetrating the interlayer insulating film, a plurality of contact plugs embedded in the first contact holes, a first electrode contacting the contact plugs and contacting the anode region via the second contact hole, a collector region and a cathode region formed on a back surface of the semiconductor substrate respectively in the first and second element regions, and a second electrode contacting the collector region and the cathode region.

A first trench having a first aspect ratio and a second trench having a second aspect ratio that is greater than the first trench are provided into a material stack of a semiconductor substrate and a dielectric material. An epitaxial semiconductor material having a different lattice constant than the substrate is then grown within each of the first and second trenches. The semiconductor material which is epitaxially formed in the first trench has an upper semiconductor material portion that is entirely defect free, while the semiconductor material which is epitaxially formed in the second trench has defects that randomly propagate to the topmost surface of the semiconductor material. At least one semiconductor device is then formed on each epitaxially grown semiconductor material. The at least one semiconductor device located on the epitaxially grown semiconductor material formed in the second trench is a physical unclonable function device.

A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes in the diode string. The remaining diodes are formed on a top layer placed on top of the bottom layer. The diode string further comprises a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the top layer to form a three dimensional (3D) structure of the diode string.

Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states; a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material. In some embodiments, the first diode is a Schottky diode having a semiconductor anode and a metal cathode and the second diode is a Schottky diode having a metal anode and a semiconductor cathode.