A method of manufacturing a fin diode structure includes providing a substrate, forming a doped well in said substrate, forming at least one doped region of first conductivity type or at least one doped region of second doped type in said doped well, performing an etching process to said doped region of first conductivity type or said doped region of second conductivity type to form a plurality of fins on said doped region of first conductivity type or on said doped region of second conductivity type, forming shallow trench isolations between said fins, and performing a doping process to said fins to form fins of first conductivity type and fins of second conductivity type.

Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.

A method of producing a semiconductor device is disclosed in which, after proton implantation is performed, a hydrogen-induced donor is formed by a furnace annealing process to form an n-type field stop layer. A disorder generated in a proton passage region is reduced by a laser annealing process to form an n-type disorder reduction region. As such, the n-type field stop layer and the n-type disorder reduction region are formed by the proton implantation. Therefore, it is possible to provide a stable and inexpensive semiconductor device which has low conduction resistance and can improve electrical characteristics, such as a leakage current, and a method for producing the semiconductor device.

A diode is formed in an active region. The diode includes a P-type component embedded in a first portion of the active region, an N-type component embedded in a second portion of the active region, and an undoped component disposed between the P-type component and the N-type component. An interconnect structure is formed over a first side of the diode. Different portions of the interconnect structure are electrically coupled to the P-type component and the N-type component, respectively. One or more openings are etched through a dielectric structure disposed over a second side of the diode opposite the first side. A dopant material is implanted into the active region through the one or more openings. The one or more openings are filled with a conductive material.

Provided a semiconductor device including: a semiconductor layer with an extended depletion layer; and an electrode disposed on the semiconductor layer directly or via another layer, the semiconductor layer including a first region containing, as a major component, a crystalline oxide semiconductor containing gallium, and a second region containing, as a major component, an oxide containing gallium, the second region including a linear crystal defect region in a cross section perpendicular to an upper surface of the semiconductor layer.

In one aspect, a diode comprises: a semiconductor layer having a first side and a second side opposite the first side, the semiconductor layer having a thickness between the first side and the second side, the thickness of the semiconductor layer being based on a mean free path of a charge carrier emitted into the semiconductor layer; a first metal layer deposited on the first side of the semiconductor layer; and a second metal layer deposited on the second side of the semiconductor layer.

High frequency power diode including a semiconductor wafer having first and second main sides, a first layer of a first conductivity type formed on the first main side, a second layer of a second conductivity type formed on the second main side and a third layer of the second conductivity type formed between the first layer and the second layer. The first layer has a dopant concentration decreasing from 10.sup.19 cm.sup.3 or more adjacent to the first main side of the wafer to 1.5.Math.10.sup.15 cm.sup.3 or less at an interface of the first layer with the third layer. The second layer has a dopant concentration decreasing from 10.sup.19 cm.sup.3 or more adjacent to the second main side of the wafer to 1.5.Math.10.sup.15 cm.sup.3 at an interface of the second layer with the third layer and the third layer has a dopant concentration of 1.5.Math.10.sup.15 cm.sup.3 or less.

The process is based upon the steps of: forming a trench in a body including a substrate and at least one insulating layer; and depositing a metal layer above the body for closing the open end or mouth of the trench. The trench is formed by selectively etching the body, wherein the reaction by-products deposit on the walls of the trench and form a passivation layer along the walls of the trench and a restriction element in proximity of the mouth of the trench.

Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

Methods to connect to back-plate (BP) or well contacts or diode junctions through a RMG electrode in FDSOI technology based devices and the resulting devices are disclosed. Embodiments include providing a polysilicon dummy gate electrode between spacers and extending over a BP, an active area of a transistor, and a shallow-trench-isolation (STI) region therebetween; providing an interlayer dielectric surrounding the spacers and polysilicon dummy gate electrode; removing the polysilicon dummy gate electrode creating a cavity between the spacers; forming a high-k dielectric layer and a work-function (WF) metal layer in the cavity; removing a section of the WF metal layer, high-k dielectric layer, and STI region exposing an upper surface of the BP; filling the cavity with a metal forming a replacement metal gate electrode; and planarizing the metal down to an upper surface of the spacers.