Semiconductor devices and methods of forming the same are provided. A semiconductor device includes a substrate having a fin. A first nanowire is disposed on the fin and a second nanowire is disposed on the fin, the second nanowire being laterally separated from the first nanowire. A gate structure extends around the first nanowire and the second nanowire. The gate structure also extends over a top surface of the fin. The first nanowire, the second nanowire, and the fin form a channel of a transistor.

A method for manufacturing a semiconductor device comprises epitaxially growing a plurality of silicon layers and compressively strained silicon germanium (SiGe) layers on a substrate in a stacked configuration, wherein the silicon layers and compressively strained SiGe layers are alternately stacked on each other starting with a silicon layer on a bottom of the stacked configuration, patterning the stacked configuration to a first width, selectively removing a portion of each of the silicon layers in the stacked configuration to reduce the silicon layers to a second width less than the first width, forming an oxide layer on the compressively strained SiGe layers of the stacked configuration, wherein forming the oxide layer comprises fully oxidizing the silicon layers so that portions of the oxide layer are formed in place of each fully oxidized silicon layer, and removing part of the oxide layer while maintaining at least part of the portions of the oxide layer formed in place of each fully oxidized silicon layer, wherein the compressively strained SiGe layers are anchored to one another and a compressive strain is maintained in each of the compressively strained SiGe layers.

A method for manufacturing a semiconductor device comprises epitaxially growing a plurality of silicon layers and compressively strained silicon germanium (SiGe) layers on a substrate in a stacked configuration, wherein the silicon layers and compressively strained SiGe layers are alternately stacked on each other starting with a silicon layer on a bottom of the stacked configuration, patterning the stacked configuration to a first width, selectively removing a portion of each of the silicon layers in the stacked configuration to reduce the silicon layers to a second width less than the first width, forming an oxide layer on the compressively strained SiGe layers of the stacked configuration, wherein forming the oxide layer comprises fully oxidizing the silicon layers so that portions of the oxide layer are formed in place of each fully oxidized silicon layer, and removing part of the oxide layer while maintaining at least part of the portions of the oxide layer formed in place of each fully oxidized silicon layer, wherein the compressively strained SiGe layers are anchored to one another and a compressive strain is maintained in each of the compressively strained SiGe layers.

A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.

The present disclosure provides a thin film transistor, a method for manufacturing the same, a thin film transistor assembly, an array substrate and a display apparatus. The thin film transistor comprises: a substrate; a gate electrode, a gate insulation portion, a semiconductor portion, a source electrode and a drain electrode, the gate insulation portion separating the semiconductor portion from the gate electrode, and the source electrode and the drain electrode being connected to the semiconductor portion, wherein a projection of the gate electrode onto the substrate and that of the semiconductor portion onto the substrate are not overlapped with each other.

A semiconductor device includes a fin-shaped silicon layer on a silicon substrate surface. The fin-shaped silicon layer has a longitudinal axis extending in a first direction parallel to the surface and a first insulating film is around the fin-shaped silicon layer. A pillar-shaped silicon layer is on the fin-shaped silicon layer, and a pillar diameter of the bottom of the pillar-shaped silicon layer is equal to a fin width of the top of the fin-shaped silicon layer. The pillar diameter and the fin width are parallel to the surface. A gate insulating film is around the pillar-shaped silicon layer and a metal gate electrode is around the gate insulating film. A metal gate wiring is connected to the metal gate electrode and has a longitudinal axis extending in a second direction parallel to the surface and perpendicular to the first direction of the longitudinal axis of the fin-shaped silicon layer.

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. A structure includes a relaxed substrate including a bulk material, a strained layer directly on the relaxed substrate, where a strain of the strained layer is not induced by the relaxed substrate, and a transistor formed on the strained layer.

A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of mono crystalline silicon on the surface of a semi conductive substrate, and forming a thin film of insulative material over the epitaxial layer. A second epitaxial layer is selectively, grown on the exposed surface of the initial epitaxially grown crystal layer, and a thin insulative film is deposited over the second epitaxial layer. Additional epitaxial layers are added as desired to provide a vertical structure of a desired height comprising multiple layers of single silicon crystals, each epitaxial layer have insulated sidewalls, with the uppermost epitaxial layer also with an insulated top surface.

A method of fabricating a vertical transistor is provided, the method including providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate, an impurity layer of n-type or p-type over the semiconductor substrate, a first hard mask layer over the semiconductor layer, a first dielectric layer over the first hard mask layer, a second hard mask layer over the first dielectric layer, a second dielectric layer over the second hard mask layer and a protective layer over the second dielectric layer. The method further includes patterning the second dielectric layer and protective layer, the patterning forming an opening therein, forming a wrap-around spacer on an inner sidewall of the opening, the forming leaving a smaller opening, forming a vertical channel, and setting a gate length of a wrap-around gate by removing an outer portion of the structure.