A device includes a plurality of semiconductor fins extending from a substrate. A plurality of first source/drain regions are epitaxially grown from first regions of the semiconductor fins. Adjacent two of the plurality of first source/drain regions grown from adjacent two of the plurality of semiconductor fins are spaced apart by an isolation dielectric. A gate structure laterally surrounds second regions of the plurality of semiconductor fins above the first regions of the plurality of semiconductor fins. A plurality of second source/drain regions are over third regions of the plurality of semiconductor fins above the second regions of the plurality of semiconductor fins.

A method includes forming a first transistor and a second transistor over a semiconductor substrate, wherein the first transistor and the second transistor are vertically stacked. The method further includes exposing a backside of a first gate stack of the first transistor; forming a backside gate etch stop layer (ESL) on the backside of the first gate stack; patterning a contact opening through the backside gate ESL to expose the first gate stack; and forming a backside gate contact in the contact opening. The backside gate contact extends through the backside gate ESL to electrically connect to the first gate stack.

A vertical semiconductor device with a continuous gate length and a method of manufacturing the same, and an electronic apparatus including the same. The semiconductor device includes: a semiconductor base on a substrate; first and second vertical channel portions on the semiconductor base, where the first and second vertical channel portions are vertical relative to the substrate, protrude from the semiconductor base, are spaced apart from in a first direction and self-aligned with each other, and the semiconductor base extends continuously between the first and second vertical channel portions; a first source/drain portion and a second source/drain portion on the first vertical channel portion and the second vertical channel portion, respectively; and a gate stack at least partially on the first vertical channel portion, the semiconductor base, and the second vertical channel portion to define a continuous channel between the first source/drain portion and the second source/drain portion.

A semiconductor structure includes a substrate, an oxide layer disposed over the substrate, a stack of semiconductor layers disposed over the oxide layer, and an epitaxial source/drain (S/D) feature disposed adjacent to the stack of semiconductor layers. A portion of the epitaxial S/D feature is horizontally surrounded by the oxide layer.

A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. The gate electrode includes a first work function metal; a second work function metal over the first work function metal; and a first metal residue at an interface between the first work function metal and the second work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal.

A semiconductor structure includes a base structure having a conductive feature therein, a transistor disposed above the base structure, a capacitor disposed on the transistor, and an interconnecting routing that interconnects the second electrode with the conductive feature. The transistor includes a gate electrode, a gate dielectric, a channel spaced apart from the gate electrode through the gate dielectric, and two contact structures connected to the channel and spaced apart from each other. Each of the two contact structures includes a main body, and a protection layer that includes a transition metal which is one of elements of groups 3 to 12 in periods 5 to 7, elements of lanthanide series, and elements of actinide series. The capacitor includes a first electrode connected to one of the two contact structures of the transistor, a second electrode, and a dielectric interposed between the first electrode and the second electrode.

A semiconductor device is provided. The semiconductor device includes: an active pattern provided on a substrate having an upper surface; an insulation pattern provided above the substrate and contacting an upper surface of the active pattern; channels spaced apart from each other along a direction perpendicular to the upper surface of the substrate, each of the channels including a material provided in the active pattern; and a gate structure contacting an upper surface of the insulation pattern, an upper surface of the channels, a lower surface of the channels, and sidewalls of the channels opposite to each other. A first distance between an upper surface of the active pattern and a lowermost one of the channels is greater than a second distance between an upper surface of one of the channels and a lower surface of an adjacent channel.

A semiconductor device includes a substrate, an isolation structure on the substrate, a fin protruding from the substrate and through the isolation structure, a gate stack engaging the fin, and a gate spacer on sidewalls of the gate stack. The gate spacer includes an inner sidewall facing the gate stack and an outer sidewall opposing the inner sidewall. The inner sidewall has a first height measured from a top surface of the fin and a bowed structure in a top portion of the inner sidewall. The bowed structure extends towards the gate stack for a first lateral distance measured from a middle point of the inner sidewall. The first lateral distance is less than about 8% of the first height.

Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line in a direction parallel to a backside surface of the first dielectric layer.

A semiconductor device includes a substrate, a semiconductor channel region over the substrate, a gate stack engaging the semiconductor channel region, and a gate spacer extending on a sidewall of the gate stack. The gate spacer includes an inner sidewall interfacing the gate stack and an outer sidewall opposing the inner sidewall. In a cross-sectional view along a lengthwise direction of the semiconductor channel region the inner sidewall has a footing structure in a bottom portion of the inner sidewall. The footing structure extends towards the gate stack. The semiconductor device also includes a source/drain feature abutting the semiconductor channel region and a dielectric layer on the source/drain feature. A top surface of the dielectric layer is declined towards its center.