A polycrystalline silicon thin-film transistor includes a substrate; an isolation layer formed on the substrate; and a polycrystalline silicon active layer formed on the substrate and the isolation layer, with two source-drain ion implantation regions being formed at both sides of the active layer, wherein the edges at both ends of the isolation layer are within the edges at both ends of the active layer. In the polycrystalline silicon thin-film transistor and the method for manufacturing the same, it is possible to increase the grain size of the active layer, improve the grain uniformity in a channel region thereof, effectively prevent deterioration of characteristics of the active layer caused by backlight irradiation, and improve the reliability of the device.

An array substrate is disclosed. The array substrate includes a substrate, a first film layer on a side surface of the substrate, an insulation layer on the side surface of the substrate, an electrostatic charge dispersion layer on the side surface of the substrate, and a second film layer arranged on the side surface of the substrate. The first film layer, the insulation layer, the electrostatic charge dispersion layer, and the second film layer are sequentially arranged on the substrate. In addition, the insulation layer and the electrostatic charge dispersion layer include via holes, the second film layer is electrically connected with the first film layer through the via holes, and the electrostatic charge dispersion layer is in a same profile as the second film layer.

An array substrate, a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof are disclosed. The method for manufacturing the TFT comprises: forming a pattern of an active layer and a gate insulating layer provided with a metal film on a base substrate; patterning the metal film by one patterning process, and forming patterns of a gate electrode, a source electrode, a drain electrode, a gate line and a data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole, a drain contact hole and a bridge structure contact hole; and forming a transparent conductive film on the base substrate, and removing partial transparent conductive film to form a source contact portion, a drain contact portion (214), a pixel electrode and a bridge structure. The manufacturing method can reduce the number of the patterning processes.

A display device includes two or more transistors in one pixel, and the two or more transistors include a first transistor of which a channel semiconductor layer is polycrystalline silicon, and a second transistor of which a channel semiconductor layer is an oxide semiconductor.

Oxide layers which contain at least one metal element that is the same as that contained in an oxide semiconductor layer including a channel are formed in contact with the top surface and the bottom surface of the oxide semiconductor layer, whereby an interface state is not likely to be generated at each of an upper interface and a lower interface of the oxide semiconductor layer. Further, it is preferable that an oxide layer, which is formed using a material and a method similar to those of the oxide layers be formed over the oxide layers Accordingly, the interface state hardly influences the movement of electrons.

Provided are a thin film transistor (TFT) substrate, a display device, and a method of forming the TFT. A TFT substrate includes: a first TFT including: a polycrystalline semiconductor (PS) layer, a first gate electrode (GE) overlapping the PS layer, a nitride layer (NL) on the first GE, an oxide layer (OL) on the NL, and a first source electrode and a first drain electrode on the OL, and a second TFT including: a second GE on a same layer as the first GE, a hydrogen collecting layer between the second GE and the NL, an oxide semiconductor (OS) layer on the OL, a second source electrode and a second drain electrode contacting respective sides of the OS layer, wherein the first TFT and the second TFT are disposed on a same substrate, and wherein the NL includes an opening exposing the hydrogen collecting layer of the second TFT.

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a semiconductor layer, a gate electrode on the semiconductor layer, a first insulating layer between the semiconductor layer and the gate electrode; a second insulating layer on the gate electrode, source and drain electrodes corresponding to both ends of the semiconductor layer and disposed on the second insulating layer, and a doping layer disposed along contact holes of the first and second insulating layers, which expose the both ends of the semiconductor layer, such as, between the both ends of the semiconductor layer and the source and drain electrodes.

Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.

A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

The present invention provides a manufacture method of a LTPS thin film transistor and a LTPS thin film transistor. The gate isolation layer is first etched to form the recess, and then the gate is formed on the recess so that the width of the gate is slightly larger than the width of the recess. Then, the active layer is implemented with ion implantation to form the source contact region, the drain contact region, the channel region and one transition region at least located between the drain contact region and the channel region. The gate isolation layer above the transition region is thicker than the channel region and can shield a part of the gate electrical field to make the carrier density here lower than the channel region to form a transition.

The present disclosure relates to a LTPS TFT unit for liquid crystal modules and the manufacturing method thereof. The manufacturing method includes: forming a SiNx layer on a glass substrate; forming a SiOx layer and an a-Si layer on the SiNx layer in sequence; scanning the a-Si layer by laser beams to remove hydrogen within the a-Si layer; adopting excimer laser to re-crystallization anneal the a-Si layer to form the polysilicon layer; forming a gate insulation layer on the polysilicon layer; forming a gate on the gate insulation layer; and forming a drain insulation layer on the gate.