A manufacturing method for an array substrate is provided in the present invention. The method comprises: forming a Poly-Silicon layer on a glass substrate; forming heavily doped regions by performing heavily doping and acticvation process at both sides of the Poly-Silicon layer; forming a souce/a drain of a first metal layer growing on the heavily doped region; forming a gate of both a gate insulator and a second metal layer growing sequentially on the Poly-Silicon layer, wherein, a material of the second metal layer is aluminum. The activation technology process can be improved in the present invention to reduce RC delay in metal wires of product and then further to achieve large sizes for products.

A thin film transistor array panel according to an exemplary embodiment of the present invention includes: an insulating substrate; a polycrystal semiconductor layer formed on the insulating substrate; a buffer layer formed below the polycrystal semiconductor layer and containing fluorine; a gate electrode overlapping the polycrystal semiconductor layer; a source electrode and a drain electrode overlapping the polycrystal semiconductor layer and separated from each other; and a pixel electrode electrically connected to the drain electrode.

A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

The present invention provides a manufacture method of a TFT substrate structure and a TFT substrate structure. In the manufacture method of the TFT substrate structure according to the present invention, by adjusting the parameter of etching as manufacturing the gate, the angular surfaces are formed at the two sides of the gate, and the gate is used to be a mask to implement ion implantation to the polysilicon layer to form the n-type heavy doping area and the n-type light doping area are formed at the polysilicon layer at the same time. In the TFT structure according to the present invention, the polysilicon layer comprises n-type heavy doping areas at two sides and n-type light doping areas between the channel area of the polysilicon layer and the n-type heavy doping areas.

An array substrate, a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof are disclosed. The method for manufacturing the TFT comprises: forming a pattern of an active layer and a gate insulating layer provided with a metal film on a base substrate; patterning the metal film by one patterning process, and forming patterns of a gate electrode, a source electrode, a drain electrode, a gate line and a data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole, a drain contact hole and a bridge structure contact hole; and forming a transparent conductive film on the base substrate, and removing partial transparent conductive film to form a source contact portion, a drain contact portion (214), a pixel electrode and a bridge structure. The manufacturing method can reduce the number of the patterning processes.

The present disclosure provides an array substrate for a display device and a manufacturing method thereof. A transparent electrode pattern (ITO) may be formed between a source/drain metal pattern and a passivation layer located above the source/drain metal pattern, which are formed in a passivation hole area of a non-active area of the array substrate. Accordingly, it may be possible to prevent display failure caused by a delamination phenomenon or peel-off of a material of the passivation layer due to the lack of adhesion strength between a metal layer and the passivation layer in the passivation hole area.

The present invention is suitable to the field of electronic technology, and provides a method of manufacturing a thin film transistor and a pixel unit thereof, wherein when the thin film transistor is manufactured, the gate metal layer is used as a mask, and exposed from the back of the substrate to position the channel and the source and drain of the thin film transistor, so that the channel is self-aligned with the gate, and the source and drain are self-aligned with the gate and are symmetrical, and the thin film transistor thus manufactured has a small parasitic capacitance, and the circuit manufactured therewith is fast in operation, and less prone to occurring short circuit or open circuit. In the present invention, the characteristics that the channel is self-aligned with the gate, and the source and drain are self-aligned with the gate and are symmetrical avoid the alignment precision requirement on the mask plate in the production, thus reducing the need for the high precision lithographic apparatus, and reducing the costs and increasing the yield. In addition, the present process is suitable for manufacturing a pixel unit of a thin film transistor, the manufacturing process only requires four mask sets which do not require the critical alignment. As compared with other four mask processes which use the gray tone masks, the present process can increase the yield and reduce the costs.

The present disclosure discloses a LTPS TFT and the manufacturing method thereof. The method includes: forming a semiconductor layer and a LTPS layer on the same surface on a base layer; forming an oxide layer is formed on one side of the semiconductor layer facing away the base layer, and forming the oxide layer on one side of the LTPS layer facing away the base layer; forming a first photoresist layer of a first predetermined thickness on the oxide layer; arranging a corresponding first cobalt layer on each of the photoresist layers, a vertical projection of the first cobalt layer overlaps with the vertical projection of the corresponding first photoresist layer; doping high-concentration doping ions into a first specific area of the semiconductor layer. With such configuration, the number of the masking process is decreased and the manufacturing time is reduced.

The method for manufacturing a thin film transistor includes the processes of forming a gate electrode on a surface of a substrate, forming an insulation film on the surface of the substrate on which the gate electrode is formed, forming a first amorphous silicon layer on the surface of the substrate on which the insulation film is formed, annealing a plurality of required places separated from each other on the first amorphous silicon layer by irradiating the same with an energy beam to change the required places to a polysilicon layer, forming a second amorphous silicon layer by covering the polysilicon layer, forming an n+ silicon layer on a surface of the second amorphous silicon layer, etching the first amorphous silicon layer, the second amorphous silicon layer and the n+ silicon layer.

A display substrate includes a first switching element electrically connected to a gate line and that extends in a first direction and electrically connected to a data line that extends in a second direction crossing the first direction, an insulation layer disposed on the first switching element, a shielding electrode disposed on the insulation layer and a pixel electrode that partially overlap the shielding electrode. The shielding electrode includes a first portion that overlaps the data line and extends in the second direction and a second portion that overlaps the gate line and extends in the first direction.