Patent classifications
H10D30/0321
Manufacture method of LTPS thin film transistor and LTPS thin film transistor
The present invention provides a manufacture method of a LTPS thin film transistor and a LTPS thin film transistor. The gate isolation layer is first etched to form the recess, and then the gate is formed on the recess so that the width of the gate is slightly larger than the width of the recess. Then, the active layer is implemented with ion implantation to form the source contact region, the drain contact region, the channel region and one transition region at least located between the drain contact region and the channel region. The gate isolation layer above the transition region is thicker than the channel region and can shield a part of the gate electrical field to make the carrier density here lower than the channel region to form a transition.
Low temperature poly-silicon (LTPS) thin film transistors (TFT) units and the manufacturing method thereof
The present disclosure relates to a LTPS TFT unit for liquid crystal modules and the manufacturing method thereof. The manufacturing method includes: forming a SiNx layer on a glass substrate; forming a SiOx layer and an a-Si layer on the SiNx layer in sequence; scanning the a-Si layer by laser beams to remove hydrogen within the a-Si layer; adopting excimer laser to re-crystallization anneal the a-Si layer to form the polysilicon layer; forming a gate insulation layer on the polysilicon layer; forming a gate on the gate insulation layer; and forming a drain insulation layer on the gate.
Method of manufacturing a substrate having a crystallized layer and a laser crystallizing apparatus for the same
A method of manufacturing a substrate includes: irradiating, along a first path, a laser beam emitted from a source onto a substrate, wherein the substrate includes a target layer of the laser beam, and wherein the substrate is disposed on a stage; and irradiating, along a second path, a portion the laser beam, which was emitted from the source and reached the target layer, by reflecting the laser beam back onto the target layer using a reflection mirror. An area of a second region of the target layer is greater than an area of a first region of the target layer, wherein the laser beam is irradiated along the second path in the second region, and the laser beam is irradiated along the first path in the first region.
Thin film transistor substrate comprising a photoresist layer formed between a first dielectric layer and an amorphous silicon layer
A thin film transistor array substrate includes a pixel electrode layout area, a data electrode layout area, a transparent pixel electrode layer formed in the pixel electrode layout area, a first metal layer, a first dielectric layer, an amorphous silicon layer, a second metal layer, a second dielectric layer formed in the pixel electrode layout area and the data electrode layout area. The first dielectric layer covers the first metal layer. The amorphous silicon layer, the second metal layer and the second dielectric layer are sequentially formed on the first dielectric layer. The transparent pixel electrode layer is connected to the second metal layer through a via hole formed in the pixel electrode area of the second dielectric layer. Moreover, a method for manufacturing the thin film transistor array and a liquid crystal display including the thin film transistor array substrate also are provided.
Method of manufacturing a semiconductor device to prevent occurrence of short-channel characteristics and parasitic capacitance
Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
Optical sensing device and fabricating method thereof
An optical sensing device includes a thin film transistor disposed on a substrate, an optical sensor, a planar layer, and an organic light emitting diode. The optical sensor includes a metal electrode disposed on a gate dielectric layer of the thin film transistor and connecting to a drain electrode of the thin film transistor, an optical sensing layer disposed on the metal electrode, and a first transparent electrode disposed on the optical sensing layer. The planar layer covers at least a part of the thin film transistor and the optical sensor. The organic light emitting diode is disposed on the planar layer. The anode electrode and the cathode electrode of the organic light emitting diode are electrically coupled to a gate line and a data line respectively.
Combo amorphous and LTPS transistors
The present disclosure generally relates to an improved large area substrate thin film transistor device, and method of fabrication thereof. More specifically, amorphous and LTPS transistors are formed by first forming an amorphous silicon layer, annealing the amorphous silicon layer to form polycrystalline silicon, depositing a masking layer over a first portion of the polycrystalline silicon layer, implanting a second portion of the polycrystalline silicon layer with an amorphizing species, and removing the masking layer.
TFT SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF
A manufacturing method of a TFT substrate structure is provided, in which a graphene layer is formed on a semiconductor layer and after the formation of a second metal layer, the second metal layer is used as a shielding mask to conduct injection of fluoride ions into the graphene layer to form a modified area in a portion of the graphene layer that is located on and corresponds to a channel zone of the semiconductor layer. The modified area of the graphene layer shows a property of electrical insulation and a property of blocking moisture/oxygen so as to provide protection to the channel zone. Portions of the graphene layer that are located under source and drain electrodes are not doped with ions and preserve the excellent electrical conduction property of graphene to provide electrical connection between the source and drain electrodes and the semiconductor layer.
Thin film transistor, manufacturing method thereof, array substrate, and display device
Embodiments of the present invention disclose a manufacturing method of a thin film transistor, a thin film transistor, an array substrate and a display device. The manufacturing method of a thin film transistor includes a step of forming an active layer, and the step of forming an active layer includes: forming a first poly-silicon layer and a second poly-silicon layer on the first poly-silicon layer separately, and adding dopant ions into the second poly-silicon layer and an upper surface layer of the first poly-silicon layer. By using the manufacturing method of a thin film transistor, defect states and unstable factors of interface in the thin film transistor can be reduced, thereby improving stability of the LTPS thin film transistor and obtaining an array substrate and a display device having more stable performance.
Array substrate and display device and method for making the array substrate
An array substrate includes a substrate, driving TFTs, and switch TFTs directly on the substrate. The driving TFT includes a buffer layer, a gate, a first gate insulator layer, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and a source electrode and a drain electrode coupled to the metal oxide semiconductor layer. The switch TFT includes a buffer layer, a gate, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and a source electrode and a drain electrode coupled to the metal oxide semiconductor layer.