An organic light-emitting display apparatus includes a substrate; a thin film transistor (TFT) on the substrate; a pixel-defining layer (PDL) disposed on the TFT and comprising a first area having a first thickness and a second area having a second thickness greater than the first thickness, and a via hole in the first area; a pixel electrode disposed on at least a portion of the first area, and electrically connected to the TFT via the via hole; an intermediate layer on the pixel electrode, the intermediate layer comprising an emission layer (EML); and an opposite electrode on the intermediate layer. According to a method of manufacturing the organic light emitting display apparatus, the PDL is formed on the substrate and then the pixel electrode is formed on the first area.

A liquid crystal display (LCD) device capable of preventing impurities from permeating into a channel area of a switching element, the LCD device including: a gate electrode above a substrate; a semiconductor layer which overlaps the gate electrode; a drain electrode and a source electrode which overlap the semiconductor layer; an ohmic contact layer between the semiconductor layer and the drain electrode and between the semiconductor layer and the source electrode; a pixel electrode which is connected to one of the drain electrode and the source electrode; and a gate insulating layer between the gate electrode and the semiconductor layer, the gate insulating layer comprising fluorine. A concentration of the fluorine is decreasing, as the fluorine of the gate insulating layer being more adjacent to the substrate.

The invention provides a preparation method of a low temperature poly-silicon thin film, a preparation method of a low temperature poly-silicon thin film transistor, and a laser crystallization apparatus, and belongs to the technical field of display. The preparation method of a low temperature poly-silicon thin film of the invention comprises: forming an amorphous silicon thin film on a transparent substrate; and performing laser annealing on said amorphous silicon thin film from a side of said amorphous silicon thin film departing from said substrate, and performing laser irradiation from a side of said substrate departing from said amorphous silicon thin film, to form a low temperature poly-silicon thin film. The preparation method of a low temperature poly-silicon thin film of the invention may not only perform laser annealing on an amorphous silicon thin film form a side of the amorphous silicon thin film departing from the substrate, but also perform laser irradiation from a side of the substrate departing from the amorphous silicon thin film, and the temperature of the amorphous silicon thin film can be retained by performing laser irradiation from a side of the substrate departing from the amorphous silicon thin film. In this way, the crystallization period of poly-silicon may be elongated, and it is possible to obtain crystal grains with larger sizes, to increase carrier mobility, and to reduce drain current.

The present invention provides an array substrate and a manufacturing method thereof. Etching stop patterns or auxiliary conductive patterns of a patterned auxiliary conductive layer are disposed corresponding to heavily doped regions of a patterned semiconductor layer, and source/drain electrodes may be electrically connected to the heavily doped regions via the etching stop patterns or the auxiliary conductive patterns. The production yield and the uniformity of electrical properties may be enhanced accordingly.

According to one embodiment, a display device includes an underlying insulation layer formed on a surface of a resin layer, and a thin-film transistor formed above the surface of the resin layer via the underlying insulation layer. The underlying insulation layer includes a three-layer multilayer structure of a first silicon oxide film, a silicon nitride film formed above the first silicon oxide film, and a second silicon oxide film formed above the silicon nitride film.

In accordance with some embodiments of the disclosed subject of matter, a TFT array substrate, a method for fabricating the TFT array substrate, and a display panel that comprises the TFT array substrate are provided. In some embodiments, the TFT array substrate comprises: a substrate; an active layer comprising a first region, a source region, a drain region, and a second region between the drain region and the first region; a gate electrode above the first insulating layer, wherein the gate electrode substantially covers the first region; and a first light-shielding layer that overlaps with the first region and substantially covers the second region.

A thin film transistor array panel includes a first conductive layer including a gate electrode; a channel layer disposed over the gate; and a second conductive layer disposed over the channel layer. The second conductive layer includes a multi-layered portion defining a source electrode and a drain electrode, which includes a first sub-layer, a second sub-layer, and a third sub-layer sequentially disposed one over another. Both the third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.

A method of providing a conducting structure over a substrate, which comprises: disposing a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio; performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein; disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material; disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and patterning the multi-layered conductive structure to generate a composite lateral etch profile.

Provided are a display apparatus and a manufacturing method of the same. The display apparatus includes: a counter substrate, and an active matrix substrate including a pixel area. The active matrix substrate includes, in a non-transmissive region of each pixel, a transparent substrate, a polycrystalline silicon film, a gate insulating film, a gate electrode, an interlayer insulating film, and a drain layer including patterned conductive films, and includes, in a transparent region of each pixel, the transparent substrate, the gate insulating film and the interlayer insulating film. The interlayer insulating film includes zones where the interlayer insulating film is thinner than a part of the interlayer insulating film at the middle of each transmissive region. The zones are each located so as to extend between the neighboring patterned conductive films and are further located so as not to overlap with the transmissive regions and regions laid over LDD portions of the polycrystalline silicon film.

Embodiments of the disclosure provide a thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device. The thin film transistor comprises a substrate (1), and a gate electrode (2), a source electrode (41) and a drain electrode (42) provided on the substrate. A projection of a gap between the source electrode (41) and the drain electrode (42) on the substrate (1) coincides with a projection of the gate electrode (2) on the substrate (1).