Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.

A lateral diffused semiconductor device is disclosed, including: a substrate; a first isolation and a second isolation comprising at least portions disposed in the substrate to define an active area; a first drift region and a second drift region disposed in the active area, wherein the first drift region is disposed in the second drift region; a gate structure on the substrate; a source region in the first drift region; a drain region in the second drift region; and a ring-shaped field plate on the substrate, wherein the ring-shaped field plate surrounds at least one of the source and the drain region.

A field-effect transistor (a GaN-based HFET) includes a gate electrode, a gate electrode pad, a first wiring line connecting one end of the gate electrode and the gate electrode pad, a second wiring line connecting the other end of the gate electrode and the gate electrode pad, and a resistance element that is connected to the first wiring line and is capable of adjusting the impedance of the first wiring line.

An object of the present invention is to provide a semiconductor device capable of eliminating unevenness of current distribution in a plane. A semiconductor device according to the present invention is a semiconductor device including a transistor cell region where a plurality of transistor cells is arranged on a semiconductor substrate, the semiconductor device including an electrode pad which is arranged avoiding the transistor cell region on the semiconductor substrate and is electrically connected to a one-side current electrode of each of the cells, in which the transistor cell region contains a plurality of regions each of which has a different current drive capability from each other depending on a distance from the electrode pad.

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

A method for manufacturing an isolation structure integrated with semiconductor device includes following steps. A substrate is provided. A plurality of trenched gates is formed in the substrate. A first insulating layer and a second insulating layer are sequentially deposited on the substrate. A first etching process is performed to remove portions of the second insulating layer to expose portions of the first insulating layer. A second etching process is then performed to remove the exposed second insulating layer to expose the trenched gates and to define at least an active region.

High voltage devices and methods for forming a high voltage device are disclosed. The high voltage device includes a substrate prepared with a device isolation region. The device isolation region defines a device region. The device region includes at least first and second source/drain regions and a gate region defined thereon. A device well is disposed in the device region. The device well encompasses the at least first and second source/drain regions. A primary gate and at least one secondary gate adjacent to the primary gate are disposed in the gate region. The at least first and second source/drain regions are displaced from first and second sides of the primary gate.

An object of the present invention is to further improve electric characteristics such as ON-resistance or an ON-breakdown voltage in a semiconductor device having a lateral MOS transistor. In a semiconductor device having a lateral MOS transistor, a buried electrode is formed at a part of an isolation insulating film located between a drain region and a gate electrode. The buried electrode includes a buried part. The buried part is formed from the surface of the isolation insulating film up to a depth corresponding to a thickness thinner than that of the isolation insulating film. The buried electrode is electrically coupled to the drain region.

Under one aspect, a power Schottky diode includes a cathode; a semiconductor disposed over the cathode, the semiconductor including at least a first region and a second region, the second region defining a guard ring; an anode disposed over the first region and at least a portion of the guard ring, the anode including a metal, a junction between the anode and the first region defining a Schottky barrier; and an oxide disposed over the guard ring. Additionally, the power Schottky diode can include a resistive material disposed over at least a portion of the guard ring and at least a portion of the oxide. The resistive material can inhibit a flow of holes from the guard ring to the anode following a heavy ion strike to the guard ring. The anode further can be disposed over at least a portion of, or the entirety of, the resistive material.