Integrated circuit structures having backside contact stitching are described. In an example, an integrated circuit structure includes a first plurality of horizontally stacked nanowires laterally spaced apart from a second plurality of horizontally stacked nanowires. First and second epitaxial source or drain structure are at respective ends of the first and second pluralities of horizontally stacked nanowires. A conductive contact structure is beneath and in contact with the first epitaxial source or drain structure and the second epitaxial source or drain structure, and the conductive contact structure is continuous between the first and second epitaxial source or drain structures. The conductive contact structure has a first vertical thickness beneath the first and second epitaxial source or drain structures greater than a second vertical thickness in a region between the first and second epitaxial source or drain structures.

A semiconductor device includes a substrate. An active pattern extends in a first horizontal direction on the substrate. First to third nanosheets are sequentially spaced apart from each other in a vertical direction on the active pattern. A gate electrode extends in a second horizontal direction on the active pattern and surrounds the first to third nanosheets. A source/drain region includes a first layer disposed along side walls and a bottom surface of a source/drain trench and a second layer filling the source/drain trench. The second layer includes a first lower side wall facing a side wall of the first nanosheet and an opposite second lower side wall. A lower surface connects the first and second lower side walls and extends in the first horizontal direction. The first and second lower side walls of the second layer extend to have a constant slope in opposite directions to each other.

A high electron mobility transistor (HEMT) includes a GaN epi-layer, a first passivation layer, a source electrode metal, a drain electrode metal, a gate electrode metal, and a field plate. The first passivation layer is deposited on the GaN epi-layer. The source electrode metal, the drain electrode metal, and the gate electrode are recessed into the first passivation layer and deposited on the GaN epi-layer. The source electrode metal has a source field plate with a source field plate length Lsf. The drain electrode metal has a drain field plate with a drain field plate length Ldf, wherein Ldf>Lsf. The gate electrode is situated between the source electrode metal and the drain electrode metal. The field plate is situated between the gate electrode and the drain electrode metal.

The present disclosure relates to a semiconductor device and a fabricating method thereof, includes a substrate, a gate structure, a plug hole, a plug spacer, a metal silicide layer, and a plug. The gate structure is disposed on the substrate. The plug hole is disposed within a dielectric layer to partially extended into the substrate. The plug spacer is disposed on a sidewall of the plug hole to partially expose the substrate. The metal silicide layer is disposed at a bottom of the plug hole, wherein a portion of the substrate is sandwiched between the metal silicide layer and the plug spacer. The plug is disposed in the plug hole to physically contact the portion of the substrate. Accordingly, through forming the plug spacer to precisely define the forming location and the depth of the metal silicide layer, thereby achieving the function on improving the performance of the semiconductor device.

A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl.sub.3).sub.2CH.sub.2), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.

The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-nitride layer, a gate, a connection structure, and a gate bus. The gate is disposed over the III-nitride layer. The connection structure is disposed over the gate. The gate bus extends substantially in parallel to the gate and disposed over the connection structure from a top view perspective. The gate bus is electrically connected to the gate through the connection structure.

A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.

In an embodiment, a device includes: lower semiconductor nanostructures including a first semiconductor material; a lower epitaxial source/drain region adjacent the lower semiconductor nanostructures, the lower epitaxial source/drain region having a first conductivity type; upper semiconductor nanostructures including a second semiconductor material, the second semiconductor material different from the first semiconductor material; and an upper epitaxial source/drain region adjacent the upper semiconductor nanostructures, the upper epitaxial source/drain region having a second conductivity type, the second conductivity type being opposite the first conductivity type.

A MOS transistor including a substrate, a conductive having lateral walls, drain and source regions, and spacers having an upper surface such that the spacers are buried in the substrate and are position between the conductive gate and the drain and source regions is provided. The spacers are each cuboid-shaped and have a width that is constant along the spacers height and independent from a height of the conductive gate. A device including the MOS transistor and a method of manufacture for producing a right-hand portion and a left-hand portion of a MOS transistor is also provided.