MOS TRANSISTOR HAVING SUBSTANTIALLY PARALLELPIPED-SHAPED INSULATING SPACERS

Abstract

A MOS transistor including a substrate, a conductive having lateral walls, drain and source regions, and spacers having an upper surface such that the spacers are buried in the substrate and are position between the conductive gate and the drain and source regions is provided. The spacers are each cuboid-shaped and have a width that is constant along the spacers height and independent from a height of the conductive gate. A device including the MOS transistor and a method of manufacture for producing a right-hand portion and a left-hand portion of a MOS transistor is also provided.

Claims

1. A device, comprising: a substrate; a metal oxide semiconductor (MOS) transistor including: a conductive gate having lateral walls and a first surface; drain and source regions; and spacers having an upper surface, wherein the spacers are buried in the substrate and are positioned between the conductive gate and the drain and source regions, the first surface of the conductive gate being spaced from the upper surface of the spacers.

2. The device of claim 1, wherein the substrate includes an upper surface and a lower surface opposite the upper surface, the upper surface of the spacers is in a same horizontal plane as the upper surface of the substrate.

3. The device of claim 1, wherein the conductive gate includes a second lower surface, wherein the second lower surface of the conductive gate and a lower surface of the spacers are in a same horizontal plane as the substrate.

4. The device of claim 1, wherein an upper portion of the conductive gate protrudes above a plane of the upper surface of the substrate and of the upper surface of the spacers.

5. The device of claim 1, wherein the spacers are each cuboid-shaped.

6. The device of claim 1, wherein the spacers each have a first dimension that is substantially constant along the spacers entire height and independent from a height of the conductive gate.

7. The device of claim 1, further comprising a first area of the substrate having a second dimension, wherein the first area of the substrate is located directly under the spacers.

8. The device of claim 7, wherein the second dimension of the first area of the substrate is configured to depend upon the first dimension of the spacers.

9. The device of claim 1, wherein a height of the conductive gate is greater than a height of the spacers.

10. The device of claim 1, wherein the lateral walls of the conductive gate is only partially covered with the spacers.

11. The device of claim 1, wherein the upper surface of the conductive gates has a width greater than a distance between the spacers.

12. The device of claim 1, wherein the conductive gate is configured to have a T-shaped cross-section in a horizontal plane.

13. A device, comprising: a substrate includes a first portion and a second portion, the first portion includes: a first insulating layer on the substrate; a layer of semiconductor material on the first insulating layer; a second insulating layer on the layer of semiconductor material; a first sidewall that includes the first insulating layer, the layer of semiconductor material, the second insulating layer; and the second portion is adjacent to the first portion and is a recess, the second portion includes: a first spacer on the substrate, the first spacer having a second sidewall that faces the first sidewall; a second spacer on the substrate, the second spacer having a third sidewall opposite the second sidewall; an opening between the first sidewall and the second sidewall; a first portion of conductive gate material on the first sidewall; a second portion of conductive gate material on the second sidewall; and a third portion of conductive gate material between the first and second spacers.

14. The device of claim 13, wherein a third insulating layer is on the substrate in contact with the first, second and third sidewalls.

15. The device of claim 13, wherein the first portion of the conductive gate material has a height equal to a height of the first spacer.

16. The device of claim 15, wherein the height of the first spacer corresponds to a combined thickness of the first insulating layer and the layer of semiconductor material.

17. The device of claim 13, wherein a height of the conductive gate is greater than a height of the first spacer.

18. The device of claim 13, wherein lateral walls of the third portion of the conductive gate material is partially covered by spacers.

19. A device, comprising: a first transistor, including: a first portion of a substrate; a first conductive gate having lateral walls; and first spacers buried in the first substrate on opposite sides of the first conductive gate, the first spacers having a cuboid shape; a second transistor, including: a second portion of the substrate; a second conductive gate having lateral walls; and second spacers buried in the second substrate on opposite sides of the second conductive gate, the second spacers having a cuboid shape.

20. The device of claim 19, wherein the first and second spacers have an upper surface that is in a same horizontal plane as an upper surface of the first and second portions of the substrate.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0016] FIGS. 1A to 1C very schematically show a usual spacers manufacturing method;

[0017] FIGS. 2A and 2B schematically show two embodiments of spacers;

[0018] FIGS. 3A to 3D schematically show a method of manufacturing the embodiment of FIG. 2A;

[0019] FIGS. 4A to 4G schematically show a method of manufacturing the embodiment of FIG. 2B; and

[0020] FIG. 5 schematically shows another embodiment of spacers.

DETAILED DESCRIPTION

[0021] The same elements have been designated with the same reference numerals in the various drawings and, further, the various drawings are not to scale. For clarity, only those steps and elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, the forming of the drain and source regions, including their doping, is not detailed.

[0022] In the following description, when reference is made to terms qualifying absolute positions, such as terms left, right, etc., or relative positions, such a terms top, upper, lower, etc., or to terms qualifying orientation, such as term horizontal, vertical, reference is made to the orientation of the concerned elements in the drawings. The terms approximately and substantially are used herein to designate a tolerance of plus or minus 10%, preferably of plus or minus 5%, of the value in question.

[0023] FIGS. 1A to 1C very schematically show a usual spacer manufacturing method. At the step of FIG. 1A, a gate 2 is formed on a substrate 4. At the step of FIG. 1B, a layer 6 of insulating material, for example, silicon oxide, is deposited over the structure of the step illustrated in FIG. 1A. At the step of FIG. 1C, layer 6 is anisotropically etched to form spacers 8 covering the lateral walls of gate 2.

[0024] Spacers 8 have, due to their manufacturing method, a width varying from a maximum value at the level of substrate 4 to a minimum value close to zero at the level of the upper surface of gate 2. Further, the maximum value of the width of spacers 8 is dependent on the height of gate 2.

[0025] Thus, decreasing the height of the transistors causes a decrease in the width of spacers 8, which may become a problem, according to the voltage that the transistors have to withstand. This is for example true for transistors having to withstand voltages higher than approximately 5 V.

[0026] FIGS. 2A and 2B are cross-section views schematically showing two embodiments of MOS transistors 9A, 9B located on a chip. The transistors 9A, 9B of FIGS. 2A and 2B are each located inside and on top of a substrate 12 and each comprise a gate 14, and drain and source regions 16 relatively heavily doped with respect to substrate 12. The transistors further comprise spacers 10 located between gate 14 and the source and drain regions 16 in contact with the lateral walls of the gate.

[0027] According to the described embodiments, spacers 10 each have a substantially parallelepipedal shape. More specifically, in the cases of FIGS. 2A and 2B, spacers 10 are cuboid-shaped. Thus, the width, that is, the horizontal dimension in the plane of FIGS. 2A and 2B, of each spacer is substantially constant along its entire height and independent from the height of gate 14.

[0028] Areas 18 of substrate 12, located directly under spacers 10, are protected during the doping of the source and drain regions and are thus less heavily doped than source and drain regions 16. The width of areas 18 thus depends on the width of spacers 10.

[0029] In the case of the spacers described in relation with FIGS. 2A and 2B, the height of each gate 14 is greater than the height of its spacers 10. Thus, the lateral walls of each gate 14 are only partially covered with spacers 10. Further, the width of the upper portion of each gate 14 is here greater than the distance between its spacers 10. The upper portion of each gate 14 thus partially covers the upper surface of its spacers 10. In other words, gates 14 have a T-shaped cross-section in the plane of FIGS. 2A and 2B. As a variation, each gate 14 and its spacers 10 may have the same height.

[0030] In the embodiment of FIG. 2A, spacers 10 and gate 14 are located on the substrate 12.

[0031] In the embodiment of FIG. 2B, spacers 10 are buried in substrate 12 and their upper surface is in the same horizontal plane as the upper surface of substrate 12. The lower surface of gate 14 and the lower surface of spacers 10 are in a same plane in substrate 12. In the case of the example of FIG. 2B, an upper portion of gate 14 protrudes above the plane of the upper surface of substrate 12 and of spacers 10.

[0032] FIGS. 3A to 3D are cross-section views schematically showing the result of steps of a method of manufacturing the embodiment of FIG. 2A. A right-hand portion 20 of FIGS. 3A to 3D illustrates the result of steps of manufacturing the embodiment of FIG. 2A and a left-hand portion 22 illustrates the manufacturing of other components, for example, other transistors. The structures of right-hand 20 and left-hand 22 portions are separated by an electrically-insulating trench 24.

[0033] The structure of left-hand portion 22 comprises, on a substrate 26, an insulator layer 28 and a silicon layer 30, forming an SOI or Silicon on Insulator structure. Transistors of the type in FIG. 2A may also be formed in and on a non-SOI monocrystalline semiconductor chip, such as a silicon chip.

[0034] A layer 32 of insulator, for example, of silicon nitride or of silicon nitride, is deposited over the entire structure. The thickness of insulator layer 32 is equal to the desired height of spacers 10. Insulator layer 32 is then partially etched through a mask to form two parallelepiped spacers 10 separated by the desired width of the gate and having the desired spacer dimensions.

[0035] Insulator layer 32 may also be used as a protection layer for other areas of the chip. For example, layer 32 covers and protects layer 30 of semiconductor material of the SOI structure of the left-hand portion 22 of FIG. 3A and a portion of insulating trench 24. Such a protection layer 32 is generally provided in methods of co-integration of a plurality of transistor types. Thus, an advantage of this embodiment is that it can use a manufacturing step already present for the step of FIG. 3A with only a modification of the mask.

[0036] The structure of right-hand portion 20 comprises, on substrate 26 and around the parallelepipeds forming spacers 10, a layer 31 of insulator, for example, of silicon oxide. Layer 31 will form the gate insulator of the transistor of right-hand portion 20.

[0037] FIG. 3B shows the result of a step of depositing a layer 34 of a conductive gate material, for example, polysilicon, on the structure of FIG. 3A. Gate conductor layer 34 has a thickness equal to the height of the gate desired in right-hand portion 20.

[0038] FIG. 3C shows the result of a step of depositing an etch mask, not shown, and of an etch step. The mask protects the portion of layer 34 forming gate 14, that is, the area between spacers 10. An anisotropic etching is performed to remove the portions of layer 34 which are not protected by the mask. Preferably, the mask is placed and sized so that, as shown in FIG. 3C, gate 14 totally fills the space between spacers 10 and the upper portion of the gate partially covers spacers 10.

[0039] Areas 36 of the gate material may remain at the level of the lateral walls of protection layer 32 and of spacers 10. The width of the spacers can be adjusted so that areas 36 have no influence on the operation of the formed transistor.

[0040] FIG. 3D illustrates a manufacturing step that removes the portions of the insulator layer 31 not covered by the gate 14, as well as protection layer 32 and areas 36. The other transistors of the chip are formed later on in a usual way. For example, a transistor 38 is shown in the left-hand portion of FIG. 3D.

[0041] Vias 40, connecting the different portions of the transistors of the right-hand and left-hand portions, are formed in an insulating layer 42 covering the transistors.

[0042] It is possible to add a step of epitaxial growth of the semiconductor material of layer 30 and of substrate 26 taking place before the forming of vias 40, but after the step of FIG. 3C.

[0043] An advantage of the parallelepipedal shape of spacers 10 is that, for an epitaxial growth along a height shorter than the height of spacers 10, the distance between gate 14 and the epitaxial semiconductor material remains constant all along the length of the spacers, which is not true for spacers formed by the usual method described in relation with FIG. 1. Further, the distance between gate 14 and the epitaxial semiconductor material is conditioned by the width of spacers 10, which enables to adjust the electric field in spacers 10. Indeed, the wider the spacers, the lower the electric field in the spacers.

[0044] FIGS. 4A to 4G are cross-section views schematically showing a manufacturing method of the embodiment of FIG. 2B. FIGS. 4A to 4G comprise, as previously, a right-hand portion where the transistor of FIG. 2B will be formed and a left-hand portion where another transistor will be formed.

[0045] FIG. 4A illustrates an initial manufacturing step, during which an SOI (silicon on insulator) structure is formed. The chip thus comprises a substrate 44 made of a semiconductor material, for example, silicon, covered with a layer 46 of insulator, for example, silicon oxide. Layer 46 is itself covered with a layer 48 of semiconductor material, for example, silicon. Layer 48 of semiconductor material is covered with a layer 50 of insulator.

[0046] FIG. 4B illustrates a step during which a mask 52, for example, a hard mask, is deposited over the structure of FIG. 4A. Mask 52 comprises an opening located opposite the area where the transistor of FIG. 2B will be formed, here, the right-hand portion of FIG. 4B. Layer 50 is for example removed opposite this opening. An oxidation is then performed so that the right-hand portion then only comprises substrate 44 covered with a layer 54 of insulator, for example, silicon oxide.

[0047] FIG. 4C illustrates a next manufacturing step during which insulator layer 54 of the right-hand portion is etched to form spacers 10. The distance between the two spacers is selected according to the dimensions of gate 14 of the desired transistor. The height of the spacers corresponds to the combined thickness of layer 46 and of layer 48 of semiconductor material. There may remain an insulator layer 49 above substrate 44 in the right-hand portion, around spacers 10. This layer may be removed before forming the gate oxide of the transistor by thermal growth or by deposition.

[0048] FIG. 4D shows a step of depositing an insulator layer 55 around the spacers, which will form the gate insulator, and a gate conductor material layer 56 over the entire chip. The thickness of layer 56 is equal to the desired gate height 14 of the transistor.

[0049] FIG. 4E shows a step of etching layer 56 of the gate conductor material. As at the step of FIG. 3C, the etching is performed so that layer 56 totally fills the space between spacers 10 and possibly that the upper portion of the gate partially covers the spacers.

[0050] Areas 60 and 62, made of the gate conductor material having a shape similar to that of the spacers obtained in FIGS. 1A to 1C, form on the lateral walls of the spacers (areas 62) and on the lateral wall of the left-hand portion (area 60).

[0051] FIG. 4F illustrates a next manufacturing step. The exposed portions of gate insulator layer 55 are removed and an epitaxy is carried out to grow the semiconductor material of substrate 44 up to the level of the upper surface of spacers 10, which also corresponds to the upper surface of layer 48 of semiconductor material.

[0052] FIG. 4G illustrates a subsequent manufacturing step. During this step, various usual elements are formed. For example, in FIG. 4G, an insulating trench 64 is formed between the left-hand and right-hand structures and a transistor 66 is formed in the left-hand portion. Insulating trench 64 is formed at the level of area 60 of gate conductor, to remove it. Vias 68 are then formed, in an insulating layer 70 covering the structure, to form connections.

[0053] FIG. 5 schematically shows another embodiment of a MOS transistor 9C. FIG. 5 shows same elements as FIGS. 2A and 2B, designated with the same reference numerals. The structure of FIG. 5 may be manufactured by the method of FIG. 3A to 3D or by the method of FIGS. 4A to 4G.

[0054] The two spacers 10 shown in FIG. 5 have different widths. Indeed, in the previously-described manufacturing methods, the horizontal dimensions, including the spacer width, advantageously do not depend on the gate height but only on the dimensions of the openings of the etch masks, and it is thus possible to select different widths for the spacer on the drain side and for the spacer on the source side. Further, in the embodiment of FIGS. 3A to 3D, the height of spacers 10 may be freely selected by selecting the thickness of insulator layer 32. In the embodiment of FIGS. 4A to 4G, the height of the spacers depends on the thicknesses of layers 46 of insulator 48 and of semiconductor material of the SOI structure.

[0055] An advantage of the described embodiments is that the width of the spacers does not depend on the gate height.

[0056] Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, each described gate has a height greater than the height of its spacers. Each gate 14 may however have the same height as its spacers. The upper surface of each gate is then in the same plane as the upper surface of the spacers.

[0057] Further, the described embodiments may be applied to any structure comprising MOS transistors, for example, memory cells.

[0058] In addition, any of the transistors 9A-9C may be formed in and on a non-SOI monocrystalline semiconductor chip, such as a silicon chip.

[0059] Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present disclosure. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.