A semiconductor device includes a drain electrode, a first source electrode, a second source electrode, a first gate electrode, and a second gate electrode. The first gate electrode is arranged between the first source electrode and the drain electrode. The first gate electrode extends along a first direction. The second gate electrode is arranged between the second source electrode and the drain electrode. The second gate electrode extends along the first direction. The first gate electrode is arranged above a first imaginary line substantially perpendicular to the first direction in a top view of the semiconductor device and the second gate electrode is arranged below a second imaginary line substantially perpendicular to the first direction in the top view of the semiconductor device.

A semiconductor device for power amplification includes: a source electrode, a drain electrode, and a gate electrode disposed above a semiconductor stack structure including a first nitride semiconductor layer and a second nitride semiconductor layer; and a source field plate that is disposed above the semiconductor stack structure between the gate electrode and the drain electrode, and has a same potential as a potential of the source electrode. The source field plate has a staircase shape, and even when length LF2 of an upper section is increased for electric field relaxation, an increase in parasitic capacitance Cds generated between the source field plate and a 2DEG surface is inhibited.

One aspect of the present disclosure pertains to a method of forming a semiconductor device. The method includes receiving a workpiece having a first metal gate stack over a first channel region, a second metal gate stack over a second channel region, a source/drain (S/D) feature between the first and second channel regions, and an S/D contact over the S/D feature. First and second dielectric caps are formed over the first and second metal gate stacks and a contact etch stop layer (CESL) is formed over the S/D contact and over the first and second dielectric caps. An interlayer dielectric (ILD) layer is formed over the CESL and an S/D via trench is formed through the ILD layer and the CESL. An S/D via is formed in the S/D via trench, making full surface contact with the S/D contact and partial surface contact with the first and second dielectric caps.

A semiconductor structure includes a semiconductor substrate, a first source/drain portion, a second source/drain portion, a first metal contact, a second metal contact and a first conductive carbon layer. The first and second source/drain portions are formed over the semiconductor substrate, and are spaced apart from each other. The first source/drain portion has a conductivity type different from that of the second source/drain portion. The first and second metal contacts are respectively formed on the first and second source/drain portions. The first conductive carbon layer is formed between the first source/drain portion and the first metal contact.

An apparatus includes a substrate of a first conductivity, an extended drain region of a second conductivity formed over the substrate, a body region of the first conductivity formed in the extended drain region, a source region of the second conductivity formed in the body region, a drain region of the second conductivity formed in the extended drain region, a first dielectric layer formed over the body region and the extended drain region, a second dielectric layer formed over the extended drain region, and between the first dielectric layer and the drain region, a first gate formed over the first dielectric layer, and a second gate formed over the second dielectric layer, wherein the second gate is electrically connected to the source region.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a gate structure with a first portion having a first top surface and a second portion having a second top surface, the first top surface being above the second top surface; a dielectric cap layer on top of the second portion of the gate structure, the first portion of the gate structure being embedded in the dielectric cap layer; and a gate contact being above and substantially aligned with the first portion of the gate structure. A method of forming the same is also provided.

A semiconductor device includes a semiconductor layer, a gate structure, a control-source electrode plate, and a drain electrode. The semiconductor layer has a channel region. The gate structure has a surface to contact the semiconductor layer, in which the gate structure overlaps the channel region of the semiconductor layer along a direction perpendicular to the surface of the gate structure. The control-source electrode plate is in contact with the semiconductor layer, in which the control-source electrode plate covers the gate structure and the channel region of the semiconductor layer along the direction perpendicular to the surface of the gate structure. The drain electrode is in contact with the semiconductor layer.

An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.

A field effect transistor comprising a buffer and channel layer formed successively on a substrate. A source electrode, drain electrode, and gate are all formed in electrical contact with the channel layer, with the gate between the source and drain electrodes. A spacer layer is formed on at least a portion of a surface of the channel layer between the gate and drain electrode and a field plate is formed on the spacer layer isolated from the gate and channel layer. The spacer layer is electrically connected by at least one conductive path to the source electrode, wherein the field plate reduces the peak operating electric field in the device.