A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment.

A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is patterned to form nanosheet structures. A dummy gate structure is formed over and between the nanosheet structures. An interlevel dielectric layer is formed. The dummy gate structures are removed. SG regions are blocked, and top sheets are removed from the nanosheet structures along the dummy gate trench. A bottommost sheet is released and forms a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the bottommost sheet. A gate structure is formed in and over the dummy gate trench wherein the bottommost sheet forms a device channel for the EG device.

Apparatus and methods for providing variable regulated voltages are disclosed. Variable voltage control elements can adjust a regulated voltage provided by a single voltage regulator, thereby providing a variable regulated voltage. The regulated voltage can be used in a variety of applications, for example, as a bias voltage for a power amplifier.

A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is patterned to form nanosheet structures. A dummy gate structure is formed over and between the nanosheet structures. An interlevel dielectric layer is formed. The dummy gate structures are removed. SG regions are blocked, and top sheets are removed from the nanosheet structures along the dummy gate trench. A bottommost sheet is released and forms a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the bottommost sheet. A gate structure is formed in and over the dummy gate trench wherein the bottommost sheet forms a device channel for the EG device.

Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.

Disclosed are CMOS-based devices for switching radio frequency (RF) signals and methods for biasing such devices. In certain RF devices such as mobile phones, providing different amplification modes can yield performance advantages. For example, a capability to transmit at low and high power modes typically results in an extended battery life, since the high power mode can be activated only when needed. Switching between such amplification modes can be facilitated by one or more switches formed in an integrated circuit and configured to route RF signal to different amplification paths. In certain embodiments, such RF switches can be formed as CMOS devices, and can be based on triple-well structures. In certain embodiments, an isolated well of such a triple-well structure can be provided with different bias voltages for on and off states of the switch to yield desired performance features during switching of amplification modes.

A semiconductor arrangement includes a well region and a first region disposed within the well region. The first region includes a first conductivity type. The semiconductor arrangement includes a first gate disposed above the well region on a first side of the first region. The first gate includes a first top surface facing away from the well region. The first top surface has a first top surface area. The semiconductor arrangement includes a first gate contact disposed above the first gate. The first gate contact includes a first bottom surface facing towards the well region. The first bottom surface has a first bottom surface area. The first bottom surface area covers at least about two thirds of the first top surface area.