A semiconductor device includes a first and a second switching element, a first and a second conductive member, and a capacitor. The first switching element has a first element obverse surface and a first element reverse surface facing away from each other in a first direction. The second switching element has a second element obverse surface and a second element reverse surface facing away from each other in the first direction. The first and second conductive members are spaced apart in a second direction orthogonal to the first direction. The capacitor has a first and a second connection terminal. The first and second switching elements are connected in series, forming a bridge. The first and second connection terminals are electrically connected to opposite ends of the bridge. The capacitor and the first switching element are on the first conductive member, the second switching element on the second conductive member.

Engineered quantum processing elements are disclosed. The engineered quantum processing element includes a dopant dot embedded in a semiconductor substrate. A dielectric material forms an interface with the semiconductor substrate. The dopant dot includes a plurality of dopant atoms and one or more electrons/holes confined within the dopant dot. The geometrical configuration of the plurality of dopant atoms with respect to the semiconductor substrate is engineered to achieve optimal linear hyperfine Stark coefficients. Further, aspects of the present disclosure are directed to methods of fabricating such engineered quantum processing elements.

Engineered quantum processing elements are disclosed. The engineered quantum processing element includes a dopant dot embedded in a semiconductor substrate. A dielectric material forms an interface with the semiconductor substrate. The dopant dot includes a plurality of dopant atoms and one or more electrons/holes confined within the dopant dot. The geometrical configuration of the plurality of dopant atoms with respect to the semiconductor substrate is engineered to achieve optimal linear hyperfine Stark coefficients. Further, aspects of the present disclosure are directed to methods of fabricating such engineered quantum processing elements.

Some embodiments include an integrated assembly having a first graphene-containing-material offset from a second graphene-containing-material. The first graphene-containing-material includes a first graphene-layer-stack with first metal interspersed therein. The second graphene-containing-material includes a second graphene-layer-stack with second metal interspersed therein. A conductive interconnect couples the first and second graphene-containing materials to one another.

Some embodiments include an integrated assembly having a first graphene-containing-material offset from a second graphene-containing-material. The first graphene-containing-material includes a first graphene-layer-stack with first metal interspersed therein. The second graphene-containing-material includes a second graphene-layer-stack with second metal interspersed therein. A conductive interconnect couples the first and second graphene-containing materials to one another.

The present disclosure provides a reference electrode for providing a reference potential during measurement of a property of a sample. The reference electrode comprising: a reference electrode layer; and a reference layer provided over at least a part of the reference electrode layer and defining a sample receiving region which is separated from the reference electrode layer by the reference layer. In one embodiment, the reference layer comprises fluorinated or silanized graphene and/or fluorinated or silanized graphene oxide. Alternatively, the graphene or graphene oxide are functionalised or doped so as to form a super-hydrophobic reference layer.

The present disclosure provides a reference electrode for providing a reference potential during measurement of a property of a sample. The reference electrode comprising: a reference electrode layer; and a reference layer provided over at least a part of the reference electrode layer and defining a sample receiving region which is separated from the reference electrode layer by the reference layer. In one embodiment, the reference layer comprises fluorinated or silanized graphene and/or fluorinated or silanized graphene oxide. Alternatively, the graphene or graphene oxide are functionalised or doped so as to form a super-hydrophobic reference layer.

A fin-based tunneling filed field effect transistor (TFET) includes a control gate structure and an assisting gate structure adjacent to the control gate structure. The assisting gate structure is disposed between the control gate structure and a source/drain region of the fin-based TFET. When a voltage is applied to the assisting gate structure, the assisting gate structure causes the valence band of the fin-based TFET to be raised near the junction between the source/drain region and a channel region in a semiconductor layer under the assisting gate structure. This reduces the tunneling distance between the source/drain region and the channel region, which allows for a lesser threshold voltage to be used for the control gate structure than without the assisting gate structure.

The perovskite solar cell (PSC) includes a first layer containing a conducting material coated glass plate as a substrate, a second layer containing copper doped nickel oxide, a third layer containing a perovskite, a fourth layer containing nitrogen (N)-doped graphene quantum dots, a fifth layer containing phenyl-C61-butyric acid methyl ester and a top layer including conductive layer. A method for producing the perovskite solar cell is also discussed.

A semiconductor device includes a semiconductor substrate. The semiconductor device further includes a doped well disposed over the semiconductor substrate and including a first dopant having a conductivity type different than a conductivity type of the semiconductor device. The semiconductor device further includes a first doped layer disposed within the doped well and including a second dopant having the conductivity type of the semiconductor device. The semiconductor device further includes a source region and a drain region disposed within the first doped layer. The semiconductor device further includes an isolation structure disposed adjacent to the first doped layer. The semiconductor device further includes a second doped layer disposed adjacent to the isolation structure and over the doped well. In some aspects, the second doped layer includes a third dopant having a conductivity type different than the conductivity type of the semiconductor device.