A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the X direction; first and second active regions arranged on the opposite sides of the reference potential wire in the Y direction; and a gate electrode layer extending in the Y direction in such a manner as to cross with the first and second active regions . Then, the gate electrode layer has a first gate electrode of a second conductivity type at the crossing part with the first active region, a second gate electrode of the second conductivity type at the crossing part with the second active region, and a non-doped electrode between the first gate electrode and the second gate electrode.

An integrated radio frequency (RF) circuit structure may include an active device on a first surface of an isolation layer. The integrated RF circuit structure may also include backside metallization on a second surface opposite the first surface of the isolation layer. A body of the active device is biased by the backside metallization. The integrated RF circuit structure may further include front-side metallization coupled to the backside metallization with a via. The front-side metallization is arranged distal from the backside metallization. The front-side metallization, the via, and the backside metallization may at least partially enclose the active device.

A semiconductor structure includes a semiconductor wafer having at least one semiconductor device integrated in a first device layer, a thermally conductive but electrically isolating layer on a back side of the semiconductor wafer, a front side glass on a front side of the semiconductor wafer, where the thermally conductive but electrically isolating layer is configured to dissipate heat from the at least one semiconductor device integrated in the semiconductor wafer. The thermally conductive but electrically isolating layer is selected from the group consisting of aluminum nitride, beryllium oxide, and aluminum oxide. The at least one semiconductor device is selected from the group consisting of a complementary-metal-oxide-semiconductor (CMOS) switch and a bipolar complementary-metal-oxide-semiconductor (BiCMOS) switch. The semiconductor structure also includes at least one pad opening extending from the back side of the semiconductor wafer to a contact pad.

A semiconductor device includes a first semiconductor layer; an insulation member layer formed on the first semiconductor layer; a transistor disposed in an upper portion of the insulation member layer; a first interlayer insulation film covering the transistor; a layered member including a wiring layer formed on the first interlayer insulation film and a second interlayer insulation film; and a first penetrating electrode penetrating through the insulation member layer, the first interlayer insulation film, and the layered member. The first penetrating electrode is electrically connected only to the first semiconductor layer.

Metal layout for radio-frequency (RF) switches. In some embodiments, an RF switching device can include a plurality of field-effect transistors (FETs) arranged in series to form a stack. Each of at least some of the FETs can include a source contact and a drain contact, a first group of fingers electrically connected to the source contact, and a second group of fingers electrically connected to the drain contact and arranged in an interleaved configuration with the first group of fingers. At least some of the first group of fingers and the second group of fingers can include a first metal M1 and a second metal M2 arranged in a stack. At least one of the first metal M1 and the second metal M2 can include a tapered portion to yield a current carrying capacity that varies as a function of location along a direction in which the corresponding finger extends.

Device structures and fabrication methods for a backside contact to a final substrate. An electrically-conducting connection is formed that extends through a device layer of a silicon-on-insulator substrate and partially through a buried insulator layer of the silicon-on-insulator substrate. After the electrically-conducting connection is formed, a handle wafer of the silicon-on-insulator substrate is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is coupled to the buried insulator layer such that the electrically-conducting connection is coupled with the final substrate.

A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.

An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel.