Semiconductor device, electrical device system, and method of producing semiconductor device

Abstract

A semiconductor device includes a first semiconductor layer; an insulation member layer formed on the first semiconductor layer; a transistor disposed in an upper portion of the insulation member layer; a first interlayer insulation film covering the transistor; a layered member including a wiring layer formed on the first interlayer insulation film and a second interlayer insulation film; and a first penetrating electrode penetrating through the insulation member layer, the first interlayer insulation film, and the layered member. The first penetrating electrode is electrically connected only to the first semiconductor layer.

Claims

1. A semiconductor device, comprising: a first semiconductor layer; an insulation member layer formed on the first semiconductor layer; a transistor disposed in an upper portion of the insulation member layer; a first interlayer insulation film covering the transistor; a layered member including a wiring layer formed on the first interlayer insulation film and a second interlayer insulation film; and a first penetrating electrode penetrating through the insulation member layer, the first interlayer insulation film, and the layered member, wherein said first penetrating electrode is electrically connected only to the first semiconductor layer, said first penetrating electrode includes a first wiring formed in the wiring layer and a second wiring formed on the second interlayer insulation film, and said first wiring has a width smaller than that of the second wiring.

2. The semiconductor device according to claim 1, further comprising a second semiconductor layer formed on the insulation member layer, wherein said transistor is formed on the second semiconductor layer.

3. The semiconductor device according to claim 1, further comprising a second penetrating electrode penetrating through the insulation member layer and the first interlayer insulation film, Wherein said wiring layer is connected to the transistor, and said wiring layer is connected to the first semiconductor layer through the second penetrating electrode.

4. The semiconductor device according to claim 1, further comprising a voltage applying unit, wherein said wiring layer includes a connecting portion to be connected to a positive electrode of the voltage applying unit or a reference potential.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic vertical sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention;

(2) FIG. 2 is a schematic plan view showing the configuration of the semiconductor device according to the first embodiment of the present invention;

(3) FIG. 3 is a schematic vertical sectional view No. 1 showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

(4) FIG. 4 is a schematic vertical sectional view No. 2 showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

(5) FIG. 5 is a schematic vertical sectional view No. 3 showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

(6) FIG. 6 is a schematic vertical sectional view No. 4 showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

(7) FIG. 7 is a schematic vertical sectional view No. 5 showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

(8) FIG. 8 is a schematic vertical sectional view No. 6 showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

(9) FIG. 9 is a schematic vertical sectional view No. 7 showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

(10) FIG. 10 is a schematic vertical sectional view No. 8 showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

(11) FIG. 11 is a schematic vertical sectional view No. 9 showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

(12) FIG. 12 is a schematic plan view showing a configuration of a semiconductor device according to a second embodiment of the present invention;

(13) FIG. 13 is a schematic plan view showing a radiographic X-ray equipment according to a third embodiment of the present invention;

(14) FIG. 14 is a schematic plan view showing an example of a configuration of a conventional semiconductor device; and

(15) FIG. 15 is a schematic vertical sectional view showing the example of the configuration of the conventional semiconductor device.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(16) Hereunder, preferred embodiments of the present invention will be explained with reference to the accompanying drawings.

(17) First Embodiment

(18) A semiconductor device 100 according to a first embodiment of the present invention will be explained. The semiconductor device 100 is capable of being configured as a sensor having sensitivity relative to an X-ray, a -ray, visible light, and the like. In the following description, the semiconductor device 100 will be explained as an example that functions as an X-ray sensor.

(19) First, a configuration of the semiconductor device 100 will be explained with reference to FIGS. 1 and 2. FIG. 1 is a schematic vertical sectional view showing the configuration of the semiconductor device 100 according to the first embodiment of the present invention. Further, FIG. 2 is a schematic plan view showing the configuration of the semiconductor device 100 according to the first embodiment of the present invention.

(20) As shown in FIG. 1, the semiconductor device 100 uses an SOI substrate formed of an embedded oxide film 10 laminated on an N-type semiconductor layer 11 and a P-type semiconductor layer 90 laminated on the embedded oxide film 10. The N-type semiconductor layer 11 is formed of an N-type silicon (Si) supporting substrate.

(21) In the first embodiment, an insulation film 20 and an interlayer insulation film 21 are formed on the SOI substrate. The insulation film 20 is formed of the embedded oxide film 10, a field oxide film 22 (described later), and an interlayer film 25 (described later). Further, as an periphery circuit element, a MOS-type transistor (a filed effect transistor) 40, a diode 46, a diode 48, a first substrate contact portion 42, a first substrate contact portion 44, and a second substrate contact portion 50 are formed on the SOI substrate.

(22) It should be noted that, in the first embodiment, a substrate contact portion collectively refers to a configuration including an N-type drawing out electrode region (described later) or a P-type drawing out electrode region (described later), so-called a substrate contact, in addition to a conductive member connected to the N-type drawing out electrode region or the P-type drawing out electrode region. Accordingly, the first substrate contact portion 42 and the first substrate contact portion 44 represent a partial section of a substrate contact portion 45 formed in a ring shape as shown in FIG. 2.

(23) In the first embodiment, the MOS-type transistor 40 is configured to include the P-type semiconductor layer 90; an LDD (Lightly Doped Drain) region 16; a gate oxide film 12; a gate electrode 15; a first via 222; a first conductive member 242; a second via 232; a second conductive member 252; a first via 223; a first conductive member 243; a second via 233; and a second conductive member 253. The LDD region 16 is formed between a source, a drain, and a channel of the MOS-type transistor 40. Further, the first via 222, the first conductive member 242, the second via 232, the second conductive member 252 are connected to the drain of the MOS-type transistor 40. Further, the first via 223, the first conductive member 243, the second via 233, the second conductive member 253 are connected to the source of the MOS-type transistor 40.

(24) In the first embodiment, the first conductive member 242 and the first conductive member 243 are a part of a first layer wiring portion 240 among multilayer wiring portions formed in the semiconductor device 100. Similarly, the second conductive member 252 and the second conductive member 253 are a part of a second layer wiring portion 250 among multilayer wiring portions formed in the semiconductor device 100. Other first conductive members and second conductive members are similarly configured.

(25) In the first embodiment, the circuit elements formed in the semiconductor device 100 such as the MOS-type transistor 40, the diode 46, the diode 48, and the like are connected in a specific pattern with the first layer wiring portion 240 and the second layer wiring portion 250. For example, as shown in FIG. 1, the source of the MOS-type transistor 40 is connected to an anode of the diode 46. It should be noted that the circuit elements are not limited to the direct connection shown in FIG. 1, and may be connected through other circuit element such as a diode, a resistor, a capacitor, and the like.

(26) In the first embodiment, the diode 46 is configured to include a P-type drawing out electrode region 18 formed on a main surface (a front surface) 151 of the N-type semiconductor layer 11 as a high concentration P-type region; a first via 224 connected to the P-type drawing out electrode region 18; a first conductive member 244; a second via 234; and a second conductive member 254. Further, the diode 48 is configured to include a P-type drawing out electrode region 19 formed on the main surface 151 of the N-type semiconductor layer 11 as a high concentration P-type region; a first via 226 connected to the P-type drawing out electrode region 19; a first conductive member 246; the second via 236; and the second conductive member 256. Accordingly, a diode portion for detecting an X-ray is formed through a PN connection between the P-type drawing out electrode region 18 and the N-type semiconductor layer 11, or a PN connection between the P-type drawing out electrode region 19 and the N-type semiconductor layer 11.

(27) In the first embodiment, the first substrate contact portion 42 is configured to include an N-type drawing out electrode region 181 as a high concentration N-type impurity region higher than the N-type semiconductor layer 11; a first via 221 connected to the N-type drawing out electrode region 181; a first conductive member 241; the second via 231; and the second conductive member 251. Further, the first substrate contact portion 44 is configured to include an N-type drawing out electrode region 183 as a high concentration N-type impurity region higher than the N-type semiconductor layer 11; a first via 227 connected to the N-type drawing out electrode region 183; the first conductive member 247; the second via 237; and a second conductive member 257.

(28) In the first embodiment, the second substrate contact portion 50 is configured to include an N-type drawing out electrode region 182 as a high concentration N-type impurity region higher than the N-type semiconductor layer 11; a first via 225 connected to the N-type drawing out electrode region 182; a first conductive member 245; the second via 235; and an electrode 260.

(29) As shown in FIG. 2, the electrode 260 is disposed inside a circuit element region 49 surrounded with the substrate contact portion 45. It should be noted that the electrode 260 is not connected to any via or conductive member, and becomes a floating electrode. In the first embodiment, the position of the electrode 260 inside the circuit element region 49 is not limited to the configuration shown in FIG. 2, and it is preferred that the electrode 260 is disposed at the center of the circuit element region 49 in consideration of uniformity of the effect of the electrode 260. It is also noted that other second conductive members such as the second conductive member 252, the second conductive member 253, and the like connected to the MOS-type transistor 40 are not shown in FIG. 2.

(30) In the first embodiment, a backside electrode 280 is disposed on a main surface 152 of the semiconductor device 100 opposite to the main surface 151 thereof. Similar to the N-type drawing out electrode region 181 and the N-type drawing out electrode region 183, the backside electrode 280 is configured to function as a cathode electrode of the diode 46 and the diode 48. However, it is possible to apply a bias to the diode 46 and the diode 48 only through the N-type drawing out electrode region 181 and the N-type drawing out electrode region 183. Accordingly, it is not necessary to provide the backside electrode 280 in the first embodiment.

(31) As shown in FIG. 1, a power source 30 and a ground 32 are arranged to apply a bias to the semiconductor device 100. More specifically, the second conductive member 251 of the first substrate contact portion 42, the second conductive member 257 of the first substrate contact portion 44, and the backside electrode 280 are connected to a positive electrode of the power source 30. Accordingly, a positive voltage is applied to the N-type drawing out electrode region 181, the N-type drawing out electrode region 183, and the N-type semiconductor layer 11. It should be noted that the second conductive member 251 and the second conductive member 257 are configured to function as the cathode electrode of the diode 46 and the diode 48.

(32) Further, the second conductive member 254 of the diode 46 and the second conductive member 256 of the diode 48 are connected to a negative electrode of the power source 30 and the ground 32. Accordingly, a ground potential is applied to the P-type drawing out electrode region 18 and the P-type drawing out electrode region 19. It should be noted that the second conductive member 254 and the second conductive member 256 are configured to function as the anode electrode of the diode 46 and the diode 48.

(33) In the first embodiment, when the power source 30 applies a high voltage about 100 to 300 V through the bias path described above, the N-type semiconductor layer 11 constituting the diode 46 and the diode 48 for detecting an X-ray becomes depleted. It should be noted that the power source 30 is also connected to the second conductive member 252 connected to the drain of the MOS-type transistor 40, the second conductive member 253 connected to the source of the MOS-type transistor 40, and the gate electrode 15, so that a specific bias is applied according to functions thereof.

(34) In the semiconductor device 100 according to the first embodiment, the first conductive member 245 of the second substrate contact portion 50 and the electrode 260 are not connected to any via or a metal wiring portion other than the second substrate contact portion 50. Accordingly, the second substrate contact portion 50 becomes the floating electrode in a region surrounded with the substrate contact portion 45 including the first substrate contact portion 42 and the first substrate contact portion 44.

(35) In the first embodiment, when a surge electrical current is generated due to arc discharge and the like, it is possible to release the surge electrical current to the backside surface of the SOI substrate through the second substrate contact portion 50. As a result, it is possible to prevent the semiconductor device 100 from damaging. In other words, the second substrate contact portion 50 is configured to function as a lightning rod for the semiconductor device 100.

(36) Further, as described above, in the first embodiment, it is configured such that the second substrate contact portion 50 becomes the floating electrode. Accordingly, even when the semiconductor device 100 is operating, it is possible to prevent a waste leak electrical current from being generated between the second substrate contact portion 50 and the substrate contact portion 45 or due to breakdown between the second substrate contact portion 50 and the diode 46 or the diode 48.

(37) A method of producing the semiconductor device 100 will be explained next with reference to FIGS. 3 to 11. FIGS. 3 to 11 are schematic vertical sectional views No. 1 to No. 9 showing a manufacturing process of the semiconductor device 100 according to the first embodiment of the present invention.

(38) As shown in FIG. 3, first, the SOI substrate is produced. AS an example, the SOI substrate includes the embedded oxide film 10 having a thickness of about 200 nm; a P-type semiconductor layer 9 having a thickness of about 88 nm disposed on one side of the embedded oxide film 10; and the N-type semiconductor layer 11 having a thickness of about 700 m disposed on the other side of the embedded oxide film 10. In this process, for example, the embedded oxide film 10 may be formed of a silicon dioxide (SiO.sub.2) film. Further, the P-type semiconductor layer 9 may be formed of a P-type substrate having a relative resistivity of 10 .Math.cm, and the N-type semiconductor layer 11 may be formed of an N-type substrate having a relative resistivity of 10 K.Math.cm.

(39) In the next step, a pad oxide (SiO.sub.2) film is formed on a surface of the P-type semiconductor layer 9. Then, a silicon nitride (Si.sub.3N.sub.4) film (not shown) is formed on the pad oxide film through CVD and the like. After the silicon nitride film is etched and removed from an area where the field oxide film is to be formed, the field oxide film 22 is formed with an LOCOS (Local Oxidization of Silicon) method using the silicon nitride film as a mask. Accordingly, as shown in FIG. 4, the P-type semiconductor layer 90 is formed as an active region.

(40) In the next step, the gate oxide film 12 is formed on the surface of the P-type semiconductor layer 90 and the field oxide film 22 (the entire upper surface shown in FIG. 4) through CVD and the like. Then, a poly-silicon film is deposited on the gate oxide film 12, and the poly-silicon film is patterned with photo resist. In the next step, the poly-silicon film is dry-etched (not shown), so that the gate electrode 15 is formed on the gate oxide film 12 of the P-type semiconductor layer 90 as shown in FIG. 5.

(41) In the next step, after the photo resist is removed, as shown in FIG. 6, an impurity ion of the source and the drain is implanted at a low concentration to form the LDD region 16. Further, a sidewall spacer 17 is formed on a sidewall portion of the gate electrode 15. Afterward, the impurity ion of the drain is implanted at a high concentration to form the MOS-type transistor 40.

(42) In the next step, after the MOS-type transistor 40 is formed, a photo resist is patterned on the field oxide film 22 to cover a region thereof other than a region corresponding to the N-type drawing out electrode region 181, the N-type drawing out electrode region 182, the N-type drawing out electrode region 183, the P-type drawing out electrode region 18, and the P-type drawing out electrode region 19 to be formed on the main surface 151 of the N-type semiconductor layer 11. Then, the field oxide film 22 and the N-type semiconductor layer 11 are etched with the photo resist as a mask, and the photo resist is removed.

(43) In the next step, an impurity 31P+ (phosphorous), for example, is implanted into the N-type drawing out electrode region 181 constituting the second substrate contact portion 50, and the N-type drawing out electrode region 181 and the N-type drawing out electrode region 183 constituting the first substrate contact portion 42 and the first substrate contact portion 44 as the cathode of the diode 46 and the diode 48 at an implantation energy of 60 keV and a dose amount of 5.010.sup.15 cm.sup.2. As a result, as shown in FIG. 7, the N-type drawing out electrode region 181, the N-type drawing out electrode region 182, and the N-type drawing out electrode region 183 are formed in the N-type semiconductor layer 11.

(44) In the next step, an impurity 11P+ (boron), for example, is implanted into a region for forming the P-type drawing out electrode region 18 and the P-type drawing out electrode region 19 as the anode of the diode 46 and the diode 48 at an implantation energy of 40 keV and a dose amount of 5.010.sup.15 cm.sup.2. As a result, as shown in FIG. 7, the P-type drawing out electrode region 18 and the P-type drawing out electrode region 19 are formed in the N-type semiconductor layer 11. After the P-type drawing out electrode region 18, the P-type drawing out electrode region 19, the N-type drawing out electrode region 181, the N-type drawing out electrode region 182, and the N-type drawing out electrode region 183 are formed, as shown in FIG. 7, a CVD film is deposited on the field oxide film 22 to form the interlayer film 25.

(45) In the next step, a photo resist is patterned on the interlayer film 25 to cover a region thereof other than a region corresponding to the first via 222 and the first via 223 of the MOS-type transistor 40; the first conductive member 242; the first conductive member 243; the first via 221, the first via 224, the first via 225, the first via 226, and the first via 227 of the N-type semiconductor layer 11; the first conductive member 241; the first conductive member 245; the first conductive member 246; and the first conductive member 247. Then, the field oxide film 22 and the N-type semiconductor layer 11 are etched with the photo resist as a mask, and the photo resist is removed. Accordingly, as shown in FIG. 8, first contact holes 201, 202, 203, 204, 205, 206, and 207 are formed in the interlayer film 25, the field oxide film 22, and the embedded oxide film 10. Further, a metal such as tungsten (W) is filled in the first contact holes 201, 202, 203, 204, 205, 206, and 207 through CVD and the like. Accordingly, as shown in FIG. 9, the first via 221, the first via 222, the first via 223, the first via 224, the first via 225, the first via 226, and the first via 227 are formed.

(46) In the next step, the metal layer formed on the insulation film 20 through CVD is etched to form the first conductive member 241, the first conductive member 242, the first conductive member 243, the first conductive member 244, the first conductive member 245, the first conductive member 246, and the first conductive member 247 as shown in FIG. 9. The metal for forming the first conductive members may include, for example, aluminum (Al). Afterward, the backside electrode 280 is formed on the main surface 152 of the N-type semiconductor layer 11 using aluminum (Al).

(47) In the next step, the CVD film is deposited again on the insulation film 20 to form the interlayer insulation film 21. Then, the photo resist is patterned on the interlayer insulation film 21 in a region other than a region for forming the second conductive members connected to the first conductive members. Afterward, the interlayer insulation film 21 was etched with the photo resist as a mask, and the photo resist is removed. Accordingly, as shown in FIG. 10, second contact holes 211, 212, 213, 214, 215, 216, and 217 are formed in the interlayer insulation film 21. Further, a metal such as tungsten (W) is filled in the second contact holes 211, 212, 213, 214, 215, 216, and 217 through CVD and the like. Accordingly, as shown in FIG. 11, the second via 231, the second via 232, the second via 233, the second via 234, the second via 235, the second via 236, and the second via 237 are formed.

(48) In the next step, the metal layer formed on the interlayer insulation film 21 through CVD is etched to form the second conductive member 251, the second conductive member 252, the second conductive member 253, the second conductive member 254, the second conductive member 256, the second conductive member 257, and the electrode 260 as shown in FIG. 11. The metal for forming the second conductive member 251, the second conductive member 252, the second conductive member 253, the second conductive member 254, the second conductive member 256, the second conductive member 257, and the electrode 260 may include, for example, aluminum (Al).

(49) In each step of the manufacturing process described above for producing the semiconductor device 100 according to the first embodiment, the first via 225, the first conductive member 245, the second via 235, and the electrode 260 constituting the second substrate contact portion 50 are not connected to any other vias or conductive members, so that the second substrate contact portion 50 is configured to be the floating electrode.

(50) In the manufacturing process described above for producing the semiconductor device 100 according to the first embodiment, for example, in the plasma etching process shown in FIG. 10, after the second contact holes 211, 212, 213, 214, 215, 216, and 217 are formed through etching, even if plasma is generated as indicated with a solid line arrow P shown in FIG. 10, it is possible to escape charges due to the plasma as indicated with a broken line arrow C shown in FIG. 10 from a metal stage on which a wafer of the semiconductor device 100 is placed through the second substrate contact portion 50 and the backside electrode 280. Accordingly, it is possible to prevent the wafer of the semiconductor device 100 from being damaged during the manufacturing process thereof.

(51) In the first embodiment, it should be noted that the backside electrode 280 is not necessarily provided for escaping charges caused by the plasma. Accordingly, it is not necessary to form the backside electrode 280 in the step shown in FIG. 9. Further, the backside electrode 280 may be formed in the step shown in FIG. 11, or the backside electrode 280 may not be formed after all. In the semiconductor device 100, the N-type semiconductor layer 11 is formed of the conductive material. Accordingly, even when the backside electrode 280 is not formed in the semiconductor device 100, it is possible to escape charges due to the plasma.

(52) Further, in the first embodiment, even if a lightning occurs during the manufacturing process of the semiconductor device 100, it is possible to escape the surge electrical current due to the lightning to the backside surface of the SOI substrate through the second substrate contact portion 50 as indicated with the broken line arrow C shown in FIG. 10. Accordingly, it is possible to prevent the wafer of the semiconductor device 100 from being damaged due to the lightning during the manufacturing process.

(53) In the first embodiment, the semiconductor device 100 includes the two wiring layers. The present invention is not limited thereto, and the semiconductor device 100 may includes any number of the wiring layers. When the semiconductor device 100 includes more than two wiring layers, it is possible to formed the wiring layers through repeating the steps of forming the interlayer insulation film, forming the vias, and forming the conductive members shown in FIGS. 10 and 11. When the semiconductor device 100 includes a large number of the wiring layers, it tends to increase the risk of charges due to the plasma during the plasma etching or the surge electrical current due to the lightning. Accordingly, the effect of the semiconductor device 100 of the present invention becomes more evident.

(54) In the first embodiment, the second conductive members are formed on all of the first conductive members (refer to FIG. 11). The present invention is not limited thereto. It is possible to selectively form the second conductive members on specific ones of the first conductive members that are necessary to be connected.

(55) As explained above, in the semiconductor device 100 according to the first embodiment of the present invention, it is possible to provide the semiconductor device 100, the method of producing the semiconductor device 100, and the electric device system including the semiconductor device 100 capable of preventing damage due to the external charge while suppressing the waste leak electrical current.

(56) Second Embodiment

(57) A second embodiment of the present invention will be explained next with reference to FIG. 12. FIG. 12 is a schematic plan view showing a configuration of a semiconductor device 300 according to the second embodiment of the present invention.

(58) As shown in FIG. 12, the semiconductor device 300 includes a plurality of single pixel circuits 306 arranged in an array pattern. Each of the single pixel circuits 306 includes the MOS-type transistor 40, the diode 46, and the diode 48 similar to those in the first embodiment.

(59) More specifically, as shown in FIG. 12, the single pixel circuits 306 are repeatedly arranged in a first substrate contact portion 302 in an X direction and a Y direction with a pitch P of 10 m to 50 m, thereby constituting an X-ray sensor pixel portion 304. Each of the single pixel circuits 306 includes a plurality of diodes 23 (four diodes 23 are shown in FIG. 12) as a plurality of pixels. Further, each of the single pixel circuits 306 includes a second substrate contact portion 24 (the floating electrode) disposed substantially at the center thereof.

(60) In the second embodiment, the semiconductor device 300 has the configuration described above, so that the second substrate contact portions 24 are arranged with the same interval as the single pixel circuits 306. Accordingly, over the entire surface of the semiconductor device 300, or the entire surface of the wafer during the manufacturing process of the semiconductor device 300, the second substrate contact portions 24 are uniformly arranged. As a result, it is possible to more efficiently escape charges due to the plasma during the plasma etching or the surge electrical current due to the lightning.

(61) Third Embodiment

(62) A third embodiment of the present invention will be explained next with reference to FIG. 13. FIG. 13 is a schematic plan view showing a radiographic X-ray equipment having the semiconductor device 100 according to the third embodiment of the present invention. It should be noted that the semiconductor device 100 described above is capable of being applied to various radiographic X-ray systems such as a food radiographic X-ray detection system, a mammography system, a dental radiographic X-ray detection system, and the like. In the third embodiment shown in FIG. 13, the semiconductor device 100 is applied to a food radiographic X-ray detection system 800.

(63) As shown in FIG. 13, the food radiographic X-ray detection system 800 includes an X-ray sensor 802; an X-ray source 804; a conveyor belt 801; and a PC (Personal Computer) 812. The X-ray sensor 802 includes the semiconductor device 100 in the first embodiment. More specifically, the X-ray sensor 802 may be formed of a line sensor, in which the semiconductor device 100 is arranged in line. The X-ray source 804 may be formed of an X-ray tube to generate X-rays 806. The PC 812 is configured to process an image generated with the X-ray sensor 802.

(64) In the food radiographic X-ray detection system 800, the conveyor belt 801 transports a food covered with a wrapping as a detection object 808. Then, the X-ray source 804 irradiates the X-rays 806 on the detection object 808, so that the X-ray sensor 802 detects a transmission level of the X-rays 806 thus irradiated. Afterward, the X-ray sensor 802 transmits a signal of the transmission level thus detected to the PC 812, so that the PC 812 performs the image processing. Accordingly, it is possible to detect a metal piece and the like contained in the detection object 808.

(65) As described above, in the third embodiment, the food radiographic X-ray detection system 800 includes the semiconductor device 100 in the first embodiment. Accordingly, when the food radiographic X-ray detection system 800 is operated and the semiconductor device 100 is in the operating state, it is possible to prevent the waste leak electrical current between the second substrate contact portion 50 and the first substrate contact portion 42 or the first substrate contact portion 44, or due to the breakdown between the second substrate contact portion 50 and the diode 46 or the diode 48.

(66) In the third embodiment, the food radiographic X-ray detection system 800 includes the semiconductor device 100 in the first embodiment. Alternatively, the food radiographic X-ray detection system 800 may includes the semiconductor device 300 in the second embodiment to obtain the similar effect.

(67) In the first to third embodiments described above, the semiconductor device 100 or the semiconductor device 300 is provided with the N-type semiconductor layer 11 as the semiconductor substrate. The present invention is not limited thereto, and the semiconductor device 100 or the semiconductor device 300 may be provided with a P-type semiconductor layer as the semiconductor substrate. In this case, the P-type is switched to the N-type, and vise versa.

(68) Further, in the first to third embodiments described above, the semiconductor device 100 or the semiconductor device 300 includes the MOS-type transistor 40 as the periphery circuit element. The present invention is not limited thereto, and the semiconductor device 100 or the semiconductor device 300 may include a diode, a resistor, a capacitor, and the like.

(69) The disclosure of Japanese Patent Application No. 2013-025559, filed on Feb. 13, 2013, is incorporated in the application by reference.

(70) While the invention has been explained with reference to the specific embodiments of the invention, the explanation is illustrative and the invention is limited only by the appended claims.