A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.

A low-noise amplifier structure utilizing horizontally stacked field-effect transistors (FETs) is described. The stacked FET structure includes two FETs stacked horizontally and connected in series (e.g., with a shared source/drain region). The stacked FET structure described a pitch between gates that is increased above a minimum pitch defined for a transistor region of the device. Increasing the pitch reduces a metallurgical channel length of a second FET in the stacked structure below what the metallurgical channel length would be at the minimum pitch. Reducing the metallurgical channel length improves the signal-to-noise ratio of the low-noise amplifier structure.

A semiconductor device includes a field effect transistor (FET). The FET includes a gate electrode in a gate layer. The gate electrode has a first gate length and a second gate length. The second gate length is greater than the first gate length. The FET also includes an active region in a active region layer. The active region includes a source region and a drain region. The active region layer is beneath the gate layer. The FET has a first channel under the gate electrode having the first gate length and between the source region and the drain region. The FET also has a second channel under the gate electrode having the second gate length and between the source region and the drain region.