A method of epitaxially growing nitrogen-based compound semiconductor thin films on a semiconductor substrate, which is periodically patterned with grooves. The method can provide an epitaxial growth of a first crystalline phase epitaxial film on the substrate, and block the growth of an initial crystalline phase with barrier materials prepared at the sides of the grooves. Semiconductor devices employing the epitaxial films are also disclosed.

Functionalized films are provided comprising a film of ZnO or ZnO alloy disposed over a supporting substrate and a layer of organic molecules comprising terminal carboxylic acid linkage groups, wherein the organic molecules are bound to a surface of the film of ZnO or ZnO alloy via the terminal carboxylic acid linkage groups. Thin film transistors comprising the functionalized films are also provided. The functionalized films may be formed using polycrystalline ZnO and saturated fatty acids, such as stearic acid.

An organic light-emitting display apparatus is provided. The apparatus includes an organic light-emitting diode emitting visible light, a driving thin film transistor driving the organic light-emitting diode, and a compensation thin film transistor. The compensation thin film transistor includes a compensation gate electrode, a compensation semiconductor layer, a compensation source electrode, and a compensation drain electrode. The compensation gate electrode includes a first gate electrode, and a second gate electrode electrically connected to the first gate electrode. The compensation drain electrode is electrically connected to the driving gate electrode of the driving thin film transistor. The compensation semiconductor layer includes a first semiconductor region overlapping the first gate electrode and a second semiconductor region overlapping the second gate electrode and disposed further from the compensation drain electrode than the first semiconductor region, and an area of the first semiconductor region is less than that of the second semiconductor region.

The present disclosure provides an array substrate for a display device and a manufacturing method thereof. A transparent electrode pattern (ITO) may be formed between a source/drain metal pattern and a passivation layer located above the source/drain metal pattern, which are formed in a passivation hole area of a non-active area of the array substrate. Accordingly, it may be possible to prevent display failure caused by a delamination phenomenon or peel-off of a material of the passivation layer due to the lack of adhesion strength between a metal layer and the passivation layer in the passivation hole area.

A thin-film transistor substrate and a display device comprising the same are provided which can improve display quality by reducing or preventing deterioration of the characteristics of thin-film transistors. The thin-film transistor substrate comprises thin-film transistors on a lower protective metal layer. Each thin-film transistor comprises a buffer layer, a semiconductor layer, a first insulating film, a gate electrode, a second insulating film, a source electrode and a drain electrode, and a first electrode. The lower protective metal layer is electrically connected to the gate electrode and overlaps the channel region of the semiconductor layer.

An array substrate and a display panel are provided. The array substrate includes a non-display region and a display region including a plurality of pixel unit rows arranged in a first direction and extended in a second direction. Each pixel unit row includes at least one first-pixel unit having a first width in the first direction and a second width in the second direction. At least one pixel unit row includes at least one second-pixel unit having a third width in the first direction and a fourth width in the second direction, and the at least one second-pixel unit is disposed at one end or both ends of the pixel unit row. The second width is larger than or equal to the fourth width.

A display device is disclosed, which includes: a substrate; a first conductive layer disposed on the substrate and including a gate with a gate edge parallel to a first direction; a semiconductor layer disposed on the first conductive layer; and a second conductive layer disposed on the semiconductor layer and including a drain and a data line extending along the first direction, the second conductive layer electrically connecting to the semiconductor layer, the drain including a drain edge parallel to the first direction, the gate edge located between the data line and the drain edge, and a projection of the drain on the substrate located in a projection of the semiconductor layer on the substrate. Herein, a maximum width of the semiconductor layer overlapping the gate edge along the first direction is smaller than maximum widths thereof overlapping the gate and the drain edge along the first direction.

Interconnects (34) include an inside interconnect section (40) and an outside interconnect section (41). The inside interconnect section (40) includes a first interconnect layer (42), a second interconnect layer (43), and a connection section (44) that connects the first interconnect layer (42) and the second interconnect layer (43). The outside interconnect section (41) includes a third interconnect layer (45). Of a plurality of interconnects (34), in one interconnect (X) of neighboring interconnects the second interconnect layer (43) and the third interconnect layer (45) are connected, and in another of the neighboring interconnects (Y), the first interconnect layer (42) and the third interconnect layer (45) are connected.

This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a third embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and in response producing Capture and Update signals that are input to a Programmable Switch that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a fourth embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and inputting these states to a Dual Port Router to control the at-speed operations of a circuit. Each of the embodiments may be augmented to include externally accessible Update and Capture input signals that can be selected to allow a tester to directly control the at-speed operations of a circuit. The improvements of the disclosure are achieved without requiring any additional IC pins beyond the 4 required TAP pins, except for examples showing use of additional data input pins (TDI or WPI signals), additional data output pins (TDO or WPO signals) or examples showing use of additional control input pins (Capture and Update signals). Devices including the TAP improvements can be operated compliantly in a daisy-chain arrangement with devices that don't include the TAP improvements.

The disclosure provides a manufacturing method and a structure thereof of a TFT backplane. In the manufacturing method of the TFT backplane, after a polysilicon layer (3) is formed by implanting a induced ion solid-phase crystallization into an amorphous silicon layer (3), patterning the polysilicon layer using a half-tone mask to form an island active layer (4), and at the same time, etching a upper layer portion (31) with more implanted induced ions located in the middle portion of the island active layer (4) to form a channel region, retaining the upper layer portion (31) with more implanted induced ions located in two sides of the island active layer (4) to form a source/drain contact region, it not only reduces the number of masks, but also saves a process only for implanting doped ion into the source/drain contact region, thereby simplifying the process and reducing production cost.