This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a third embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and in response producing Capture and Update signals that are input to a Programmable Switch that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a fourth embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and inputting these states to a Dual Port Router to control the at-speed operations of a circuit. Each of the embodiments may be augmented to include externally accessible Update and Capture input signals that can be selected to allow a tester to directly control the at-speed operations of a circuit. The improvements of the disclosure are achieved without requiring any additional IC pins beyond the 4 required TAP pins, except for examples showing use of additional data input pins (TDI or WPI signals), additional data output pins (TDO or WPO signals) or examples showing use of additional control input pins (Capture and Update signals). Devices including the TAP improvements can be operated compliantly in a daisy-chain arrangement with devices that don't include the TAP improvements.

A semiconductor device including: one or more pieces of first wiring having a main wiring section and a bifurcation wiring section; one or a plurality of pieces of second wiring having a trunk wiring section and a plurality of branch wiring sections within a gap region between the main wiring section and the bifurcation wiring section; one or a plurality of transistors each divided and formed into a plurality of pieces, the plurality of branch wiring sections individually functioning as a gate electrode and the one or plurality of transistors having a source region formed within the main wiring section and within the bifurcation wiring section and having a drain region formed between the plurality of branch wiring sections; and one or a plurality of pieces of third wiring electrically connected to the drain region of the one or plurality of transistors.

The present invention provides a TFT substrate structure, comprising a Switching TFT and a Driving TFT, and the Switching TFT comprises a first active layer, and the Driving TFT comprises a second active layer, and the first active layer and the second active layer are made by the same or different materials and the electrical properties of the Switching TFT and the Driving TFT are different. According to the different functions of the different TFTs, the present invention employs different working structures for the Switching TFT and the Driving TFT to respectively implement deposition and photolithography, and employs different materials for the active layers of the Switching TFT and the Driving TFT to differentiate the electrical properties of different TFTs in the TFT substrate. Accordingly, the accurate control to the OLED with lowest cost can be realized.

The present invention provides a TFT substrate structure, comprising a Switching TFT and a Driving TFT, and the Switching TFT comprises a first active layer, and the Driving TFT comprises a second active layer, and the first active layer and the second active layer are made by the same or different materials and the electrical properties of the Switching TFT and the Driving TFT are different. According to the different functions of the different TFTs, the present invention employs different working structures for the Switching TFT and the Driving TFT to respectively implement deposition and photolithography, and employs different materials for the active layers of the Switching TFT and the Driving TFT to differentiate the electrical properties of different TFTs in the TFT substrate. Accordingly, the accurate control to the OLED with lowest cost can be realized.

The present invention provides a GOA circuit based on P-type thin film transistor, comprising a plurality of GOA unit circuits which are cascade connected, and the GOA unit circuit of every stage comprises a forward-backward scan module (100), an output module (200), a pull-down holding module (300) and a pull-down module (400); the GOA unit circuit of the nth stage and the GOA unit circuit of the n+1th stage adjacent thereto are one cycle; the forward-backward scan module (100) employs the first high frequency clock signal (LCK) and the first backward high frequency clock signal (XLCK) to control the forward-backward scan of the P-type thin film transistor. The GOA circuit based on P-type thin film transistor can ease the deterioration of the thin film transistors in the forward-backward scan module, and reduce the circuit power consumption to decrease the number of the signal lines and realize the narrow frame design. Moreover, it can promote the stability of the GOA circuit and ensure the smooth output of the scan signal (G(n)).

The present application discloses a method of fabricating a polycrystalline semiconductor layer, comprising forming a heat storage layer; forming a buffer layer on the heat storage layer; forming a first amorphous semiconductor layer on a side of the buffer layer distal to the heat storage layer; and crystallizing the first amorphous semiconductor layer to form a first polycrystalline semiconductor layer.

The present disclosure relates to a LTPS TFT unit for liquid crystal modules and the manufacturing method thereof. The manufacturing method includes: forming a SiNx layer on a glass substrate; forming a SiOx layer and an a-Si layer on the SiNx layer in sequence; scanning the a-Si layer by laser beams to remove hydrogen within the a-Si layer; adopting excimer laser to re-crystallization anneal the a-Si layer to form the polysilicon layer; forming a gate insulation layer on the polysilicon layer; forming a gate on the gate insulation layer; and forming a drain insulation layer on the gate.

A first transistor, a second transistor, a third transistor, a fourth transistor are provided. In the first transistor, a first terminal is electrically connected to a first wiring; a second terminal is electrically connected to a gate terminal of the second transistor; a gate terminal is electrically connected to a fifth wiring. In the second transistor, a first terminal is electrically connected to a third wiring; a second terminal is electrically connected to a sixth wiring. In the third transistor, a first terminal is electrically connected to a second wiring; a second terminal is electrically connected to the gate terminal of the second transistor; a gate terminal is electrically connected to a fourth wiring. In the fourth transistor, a first terminal is electrically connected to the second wiring; a second terminal is electrically connected to the sixth wiring; a gate terminal is connected to the fourth wiring.

A thin film transistor array substrate includes a pixel electrode layout area, a data electrode layout area, a transparent pixel electrode layer formed in the pixel electrode layout area, a first metal layer, a first dielectric layer, an amorphous silicon layer, a second metal layer, a second dielectric layer formed in the pixel electrode layout area and the data electrode layout area. The first dielectric layer covers the first metal layer. The amorphous silicon layer, the second metal layer and the second dielectric layer are sequentially formed on the first dielectric layer. The transparent pixel electrode layer is connected to the second metal layer through a via hole formed in the pixel electrode area of the second dielectric layer. Moreover, a method for manufacturing the thin film transistor array and a liquid crystal display including the thin film transistor array substrate also are provided.

The present application discloses an array substrate comprising a first layer comprising a data line; at least one second layer comprising at least one data line overlapping area on intersections between the first layer and the at least one second layer; and a spacer layer between the first layer and the second layer. The spacer layer comprises a plurality of spacer units spaced apart from each other. Each of the plurality of spacer units is in an area corresponding to the overlapping area.