An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p.sup.+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p.sup.+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

Embodiments of the present disclosure provide a contact structure in a split-gate trench transistor device for electrically connecting the top electrode to the bottom electrode inside the trench. The transistor device comprises a semiconductor substrate and one or more trenches formed in the semiconductor substrate. The trenches are lined with insulating materials along the sidewalls inside the trenches. Each trench has a bottom electrode in lower portions of the trench and a top electrode in its upper portions. The bottom electrode and the top electrode are separated by an insulating material. A contact structure filled with conductive materials is formed in each trench in an area outside of an active region of the device to connect the top electrode and the bottom electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

Apparatus and associated methods relate to an edge-termination structure surrounding a high-voltage MOSFET for reducing a peak lateral electric field. The edge-termination structure includes a sequence of annular trenches and semiconductor pillars circumscribing the high-voltage MOSFET. Each of the annular trenches is laterally separated from the other annular trenches by one of the semiconductor pillars. Each of the annular trenches has dielectric sidewalls and a dielectric bottom electrically isolating a conductive core within each of the annular trenches from a drain-biased region of the semiconductor pillar outside of and adjacent to the annular trench. The conductive core of the innermost trench is biased, while the conductive cores of one or more outer trenches are floating. In some embodiments, a surface of an inner semiconductor pillar is biased as well. The peak lateral electric field can advantageously be reduced by physical arrangement of trenches and electrical biasing sequence.

A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.

Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, a semiconductor device includes a main vertical trench metal oxide semiconductor field effect transistor (main-MOSFET). The main-MOSFET includes a plurality of parallel main trenches, wherein the main trenches comprise a first electrode coupled to a gate of the main-MOSFET, and a plurality of main mesas between the main trenches, wherein the main mesas comprise a main source and a main body of the main-MOSFET. The semiconductor device also includes a sense-diode. The sense-diode includes a plurality of sense-diode trenches, wherein each of the sense-diode trenches comprises a portion of one of the main trenches, and a plurality of sense-diode mesas between the source-FET trenches, wherein the sense-diode mesas comprise a sense-diode anode that is electrically isolated from the main source of the main-MOSFET.

According to one embodiment, a method for manufacturing a semiconductor device comprises making a first opening, ion-implanting an impurity of a second conductivity type, and forming a third semiconductor layer of the second conductivity type. The first opening is made in a second semiconductor layer. The second semiconductor layer is provided on a first semiconductor layer. The first opening extends in a second direction. A dimension in a third direction of an upper part of the first opening is longer than a dimension in the third direction of a lower part of the first opening. The third direction is perpendicular to the first direction and the second direction. The impurity of the second conductivity type is ion-implanted into a side surface of the lower part of the first opening. The third semiconductor layer of the second conductivity type is formed in an interior of the first opening.

A semiconductor structure includes a semiconductor substrate having a gate electrode in a gate trench, a buried bus in the semiconductor substrate, the buried bus having a bus conductive filler in a bus trench, where the bus conductive filler is electrically coupled to the gate electrode. The bus conductive filler is surrounded by the gate electrode. The gate trench intersects the bus trench in the semiconductor substrate. The gate electrode includes polysilicon. The bus conductive filler includes tungsten. The semiconductor structure also includes an adhesion promotion layer interposed between the bus conductive filler and the gate electrode, where the adhesion promotion layer includes titanium and titanium nitride. The semiconductor structure also includes a dielectric layer covering the gate electrode over the semiconductor substrate, where the buried bus has a coplanar top surface with the dielectric layer.

In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.

A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.