An object is to provide a technique that can reduce energy loss during the transient On-period. A semiconductor device includes a first transistor, a second transistor, and a controller. The controller is configured to, before the first transistor enters a transient Off-state, apply a second Off-voltage lower than a first Off-voltage to the second gate, before the first transistor enters a transient On-state, turn On the second transistor, and after the first transistor is turned On, apply the first Off-voltage to the second gate to turn Off the second transistor.

Provided is a semiconductor device having transistor and diode sections. The semiconductor device comprises: a gate metal layer provided above the upper surface of a semiconductor substrate; an emitter electrode provided above the upper surface of the semiconductor substrate; a first conductivity-type emitter region provided on the semiconductor substrate upper surface side in the transistor section; a gate trench section, which is provided on the semiconductor substrate upper surface side in the transistor section, is electrically connected to the gate metal layer, and is in contact with the emitter region; an emitter trench section, which is provided on the semiconductor substrate upper surface side in the diode section, and is electrically connected to the emitter electrode; and a dummy trench section, which is provided on the semiconductor substrate upper surface side, is electrically connected to the gate metal layer, and is not in contact with the emitter region.

In a semiconductor device, on a surface of a collector layer including a compound semiconductor of a first conductor type, facing in a first direction, a base layer including a compound semiconductor of a second conductor type opposite from the first conductor type is disposed. On a partial region of a surface of the base layer facing in the first direction, at least one emitter mesa including a compound semiconductor of the first conductor type and forming a heterojunction with the base layer is disposed. A collector electrode is on a surface of the collector layer facing in a second direction opposite to the first direction. An emitter electrode is on a surface of the emitter mesa facing in the first direction. A base electrode is on a region, in the surface of the base layer facing in the first direction, on which the emitter mesa is not disposed.

A method of manufacturing a vertical RF bipolar transistor includes fabricating a structure, the structure including a collector formed in a substrate, a base arranged above the collector, an emitter arranged above the base, a sidewall spacer extending in a vertical direction on a sidewall of the emitter, a first layer, wherein a first portion of the first layer is arranged on the sidewall spacer such that in a lateral direction the sidewall spacer is between the emitter and the first layer and wherein an outer sidewall of the first portion of the first layer is exposed, wherein the first layer directly contacts the base in the vertical direction and in the lateral direction, and a conductive layer extending in the lateral direction. In the fabricated structure, a second portion of the first layer is arranged in the lateral direction between the base and the conductive layer.

A semiconductor device includes a plurality of first trenches each having a stripe-shape, extending in parallel to each other, a first mesa region, a second mesa region, a first interlayer insulating film covering the first mesa region and the second mesa region, and a first contact hole penetrating the first interlayer insulating film to the first mesa region, and extending along a longitudinal direction of the first trenches. The first mesa region includes emitter regions of a first conductivity type periodically provided along the longitudinal direction of the first trenches in a plan view, contact regions of a second conductivity type provided such that each of the emitter regions is interposed between the contact regions along the longitudinal direction in the plan view, and a base region of the second conductivity type provided immediately below the emitter regions and the contact regions.

A semiconductor device includes an insulating layer (IFL) on a semiconductor substrate (SUB), a conductive film (PL) on the insulating layer (IFL), an interlayer insulating film (IL) covering the conductive film (PL), a contact hole (CH1) in the interlayer insulating film (IL), the conductive film (PL) and the insulating layer (IFL), and a plug (PG1) embedded in the contact hole (CH1). A side surface of the interlayer insulating film (IL) is separated from a side surface of the conductive film (PL) to expose a part of an upper surface of the conductive film (PL), and a side surface of the insulating layer (IFL) is separated from the side surface of the conductive film (PL) to expose a part of a lower surface of the conductive film (PL). A distance (L1) from the lower surface of the conductive film (PL) to the bottom of the contact hole (CH1) is longer than a distance (L2) from the side surface of the conductive film (PL) to the side surface of the interlayer insulating film (IL).

Provided is a semiconductor device including: a first trench contact portion provided to an inside of a contact region; a second trench contact portion provided to an inside of an emitter region; a first plug portion of a second conductivity type, which is provided in contact with a lower end of the first trench contact portion and has a higher concentration than a base region; and a second plug portion of a second conductivity type, which is provided in contact with a lower end of the second trench contact portion, is provided to a position closer to a lower surface than the first plug portion, and has a higher concentration than the base region.

A bidirectional thyristor capable of improving (dv/dt)c capability includes first and second first-conductivity-type semiconductor layers; first and second second-conductivity-type semiconductor layers; a plurality of carrier emitting portions disposed on a third second-conductivity-type semiconductor layer; a fourth second-conductivity-type semiconductor layer; first and second electrodes; a gate electrode; and a passivation film. The plurality of carrier emitting portions are configured such that an opening is formed in the third second-conductivity-type semiconductor layer and the first first-conductivity-type semiconductor layer is located in the opening. In plan view, the carrier emitting portions are disposed between a position away from the gate electrode by a predetermined distance and an outer edge of the first electrode. The plurality of carrier emitting portions are disposed in contact with the outer edge of the first electrode which is in contact with a passivation film.

A device and methods of forming the same are described. The device includes a substrate and a first bipolar junction transistor (BJT) disposed over the substrate. The first BJT includes a first base region, a first emitter region, and a first collector region. The device further includes a second BJT disposed over the substrate adjacent the first BJT, and the second BJT includes a second base region, a second emitter region, and a second collector region. The device further includes an interconnect structure disposed over the first and second BJTs, and the interconnect structure includes a first conductive line electrically connected to the first emitter region and the second base region and a second conductive line electrically connected to the first collector region and the second collector region.

A semiconductor device includes a semiconductor substrate, a collector region having a first width formed within the semiconductor substrate and an intrinsic base region having a second width, disposed over the collector region, wherein the first width is greater than the second width. An extrinsic base region having an upper surface is formed over the collector region and electrically coupled to the intrinsic base region, wherein the extrinsic base region includes a monocrystalline region coupled to the intrinsic base region and a polycrystalline region coupled to the monocrystalline region. An emitter region is formed over the base region.