A circuit for protecting against electrostatic discharge events has a semiconductor substrate (200) of first conductivity embedding a first diode in a well (260) of opposite second conductivity, the diode's anode (111) tied to an I/O pin-to-be-protected (101) at a first voltage, and the first diode's cathode (112) connected to the first drain (123) of a first MOS transistor in the substrate. The first MOS transistor's first gate (122) is biased to a second voltage smaller than the first voltage, thereby reducing the first voltage by the amount of the second voltage. In series with the first MOS transistor is a second MOS transistor with its second drain (670) merged with the first source of the first MOS transistor, and its second source (131), together with its second gate (132), tied to ground potential (140).

A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad.

The present disclosure provides an electrostatic discharge (ESD) protection structure, an ESD protection circuit, and a chip. The ESD protection structure includes a semiconductor substrate, a first N-type well, a first P-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, and a second P-type doped portion. The semiconductor substrate includes a first integrated region. The first N-type well is located in the first integrated region. The first P-type well is located in the first integrated region. The first N-type doped portion is located in the first N-type well. The first P-type doped portion is located in the first N-type well. The second N-type doped portion is located in the first P-type well. The second P-type doped portion is located on a side of the second N-type doped portion away from the first N-type well.

A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; a first doped region of type one, doped in the well of type two; and a second doped region of type two, provided in the well of type one and the well of type two, not touching the first doped region of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device further comprises a plurality of contact trenches opened and extended to a lower part of the epitaxial layer filled with a doped polysilicon layer of a second conductivity type wherein the trenches are further surrounded by a heavy dopant region of the second conductivity type. The TVS device further includes a metal contact layer disposed on a top surface of the epitaxial layer electrically connected to a Vcc electrode wherein the metal contact layer further directly contacting the doped polysilicon layer and the heavy dopant region of the second conductivity type.

An electrostatic discharge device includes a power clamping circuit and an isolation circuit. The power clamping circuit includes a first Zener diode and a second Zener diode. A cathode of the first Zener diode is coupled to a first power supply line. An anode of the first Zener diode is coupled to an anode of the second Zener diode. A cathode of the second Zener diode is coupled to a second power supply line. The isolation circuit includes a first isolation diode and a second isolation diode. A cathode of the first isolation diode is coupled to the first power supply line. An anode of the first isolation diode is coupled to a cathode of the second isolation diode and a circuit being protected. An anode of the second isolation diode is coupled to the second power supply line.

A high-voltage bipolar semiconductor controlled rectifier (SCR) includes an emitter region having a first polarity and overlying a base region having a second polarity different from the first polarity; a collector region having the first polarity and lying under the base region; an anode region having the second polarity; a first sinker region having the first polarity and contacting the collector region, wherein the anode region is between the first sinker region and the base region; and a second sinker region having the first polarity and contacting the collector region, the second sinker region lying between the anode region and the base region, wherein an extension of the anode region extends under a portion of the second sinker region.

The disclosed technology relates to electronics, and more particularly, to protection devices that protect circuits from transient electrical events such as electrical overstress/electrostatic discharge. A protection device includes a semiconductor substrate having formed therein at least two wells and a deep well underlying and contacting the at least two wells. The device additionally includes a first PN diode formed in one of the at least two wells and having a first heavily doped region of a first conductivity type and a first heavily doped region of a second conductivity type, and includes a second PN diode formed in one of the at least two wells and having a second heavily doped region of the first conductivity type and a second heavily doped region of the second conductivity type. The device additionally includes a first PN diode and the second PN diode are electrically shorted by an electrical shorting structure to form a first plurality of serially connected diodes having a threshold voltage. The device further includes a PNPN silicon-controlled rectifier (SCR) having a trigger voltage and comprising the first heavily doped region of the first conductivity type, the at least two wells, the deep well, and the second heavily doped region of the second conductivity type.

A circuit for protecting against electrostatic discharge events has a semiconductor substrate (200) of first conductivity embedding a first diode in a well (260) of opposite second conductivity, the diode's anode (111) tied to an I/O pin-to-be-protected (101) at a first voltage, and the first diode's cathode (112) connected to the first drain (123) of a first MOS transistor in the substrate. The first MOS transistor's first gate (122) is biased to a second voltage smaller than the first voltage, thereby reducing the first voltage by the amount of the second voltage. In series with the first MOS transistor is a second MOS transistor with its second drain (670) merged with the first source of the first MOS transistor, and its second source (131), together with its second gate (132), tied to ground potential (140).

A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.